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ZL50022QCG1 参数 Datasheet PDF下载

ZL50022QCG1图片预览
型号: ZL50022QCG1
PDF下载: 下载PDF文件 查看货源
内容描述: 增强型4K的数字开关与地层4E DPLL [Enhanced 4 K Digital Switch with Stratum 4E DPLL]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 121 页 / 931 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50022  
Data Sheet  
External Read Only Address: 004CH  
15  
0
14  
0
13  
0
12  
0
11  
0
10  
0
9
0
8
7
6
5
4
3
2
1
0
SLM  
LST  
RFR2  
RFR1  
RFR0  
RES1  
RES0  
DPM1  
DPM0  
Bit  
Name  
Description  
6 - 4  
RFR2 - 0 Reference Frequency Indicator Bits  
These bits represent the frequency of the selected reference indicated by the reference  
bits (RES1 - 0) in this register.  
Frequency of the Selected  
RFR2  
RFR1  
RFR0  
Reference  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 kHz  
1.544 MHz  
2.048 MHz  
4.096 MHz  
8.192 MHz  
16.384 MHz  
19.44MHz  
Reserved  
3 - 2  
RES1 - 0 Reference Select Indicator Bits: These bits indicate which one of the four reference  
inputs (REF0 - 3 pins) is being selected by the device.  
RES1  
RES0  
Input Reference in use  
0
0
1
1
0
1
0
1
REF 0  
REF 1  
REF 2  
REF 3  
1 - 0  
DPM1 - 0 DPLL Timing Mode Status Bits:  
These bits indicate the DPLL’s timing mode status.  
DPM1  
DPM0  
DPLL Timing Mode State  
0
0
1
1
0
1
0
1
MTIE  
Normal  
Holdover  
Freerun  
Table 37 - Reference Change Status Register (RCSR) Bits - Read Only (continued)  
71  
Zarlink Semiconductor Inc.  
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