ZL50022
Data Sheet
External Read/Write Address: 0048H
Reset Value: 2C00H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LDI
15
LDI
14
LDI
13
LDI
12
LDI
11
LDI
10
LDI
9
LDI
8
LDI
7
LDI
6
LDI
5
LDI
4
LDI
3
LDI
2
LDI
1
LDI
0
Bit
Name
Description
15 - 0
LDI15 - 0 Lock Detector Interval Bits
The binary value of these bits defines the time interval that the output phase detector
must be below the lock detect threshold to declare lock. Unsigned representation of the
LDI bits is defined in 4 ms intervals.
Table 34 - Lock Detector Interval Register (LDIR) Bits
External Read/Write Address: 0049H
Reset Value: 099FH (see Note)
15
0
14
0
13
0
12
11
10
9
8
7
6
5
4
3
2
1
0
SRL
12
SRL
11
SRL
10
SRL
9
SRL
8
SRL
7
SRL
6
SRL
5
SRL
4
SRL
3
SRL
2
SRL
1
SRL
0
Bit
Name
Description
15 - 13
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
12 - 0
SRL12 - 0 Slew Rate Limit Bits
The binary value of these bits defines the maximum rate of DPLL phase change (phase
slope), where the phase represents difference between the input reference and output
feedback clock. Defined in same units as CFN (unsigned).
Note: The default value is ±56 ppm (’h099F/CFN = 56 ppm).
Table 35 - Slew Rate Limit Register (SRLR) Bits
68
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
