ZL50022
Data Sheet
External Read Only Address: 0045H
15
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FOF
14
FOF
13
FOF
12
FOF
11
FOF
10
FOF
9
FOF
8
FOF
7
FOF
6
FOF
5
FOF
4
FOF
3
FOF
2
FOF
1
FOF
0
Bit
Name
Unused
Description
Reserved. In normal functional mode, this bit is zero.
15
14 - 0
FOF14 - 0 Frequency Offset Bits: The binary value of these bits represents the current deviation
of the DPLL output from its center frequency. Defined in same units as CFN in the 2's
complement format.
Note 1: Output frequency offset, relative to master clock, will be represented as the following:
+10 ppm: CFN x 0.00001 = 440 = 01B8H
-10 ppm: CFN x (-0.00001) = -440 = 7E48H
Table 32 - Frequency Offset Register (FOR) Bits - Read Only
External Read/Write Address: 0047H
Reset Value: 000FH
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LDT
15
LDT
14
LDT
13
LDT
12
LDT
11
LDT
10
LDT
9
LDT
8
LDT
7
LDT
6
LDT
5
LDT
4
LDT
3
LDT
2
LDT
1
LDT
0
Bit
Name
LDT15 - 0 Lock Detect Threshold Bits
Description
15 - 0
The binary value of these bits defines the upper limit of the absolute phase from the
phase detector output for lock detection.
When the value of the absolute phase is less than or equal to LDT for duration of time
defined by the LDIR register, the DPLL locks.
When the value of the absolute phase is greater than LDT for duration of time defined by
the LDIR register divided by 256, the DPLL does not lock.
Note: LDT should be calculated as per the maximum expected amplitude of jitter on the active input reference
using the following formula:
LDT = MAX_EXP_JITTER (ns) x 2
15.2 (ns)
Example: If maximum expected jitter amplitude on 2.048 MHz reference is 10UI (i.e., 10 x 488.2 ns = 4882 ns)
(assuming the jitter frequency where DPLL attenuation is big), the LDT should be programmed to be (4882/15.2)
x 2 = 642 = 0282H
Table 33 - Lock Detector Threshold Register (LDTR) Bits
67
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
