ZL50022
Data Sheet
External Read/Write Address: 004BH
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
6
5
4
3
2
1
0
MTR
PRS
1
PRS
0
PMS
2
PMS
1
PMS
0
FDM
1
FDM
0
Bit
Name
Description
1 - 0
FDM1 - 0 Force DPLL Timing Mode
These bits force the DPLL into one of the valid operation modes.
FDM1
FDM0
DPLL TIMING Mode
0
0
1
1
0
1
0
1
Automatic
Normal
Holdover
Freerun
Table 36 - Reference Change Control Register (RCCR) Bits (continued)
External Read Only Address: 004CH
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
5
4
3
2
1
0
SLM
LST
RFR2
RFR1
RFR0
RES1
RES0
DPM1
DPM0
Bit
Name
Description
15 - 9
Unused
Reserved
In normal functional mode, these bits are zero.
8
7
SLM
LST
Slew Rate Limiter Status Bit
If the device sets this bit to high, the DPLL phase difference between the input and output
clocks is changing at the slew rate limit defined in the Slew Rate Limit Register (SRLR).
Lock Status Bit
If the device sets this bit to high, while the LDTR and LDIR registers are programmed
properly, the DPLL output clocks are locked to the selected input reference.
If this bit is low, the DPLL output clocks are not yet locked to the selected input reference.
Table 37 - Reference Change Status Register (RCSR) Bits - Read Only
70
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
