ZL50022
Data Sheet
External Read Only Address: 0069H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R3
R3
R3
FL
R3
FU
R2
R2
R2
FL
R2
FU
R1
R1
R1
FL
R1
FU
R0
R0
R0
FL
R0
FU
FML
FMU
FML
FMU
FML
FMU
FML
FMU
Bit
Name
Description
15
14
13
12
11
10
9
R3FML
Reference 3 Multi-period Lower Limit Fail Bit
f the device sets this bit to high, the input REF3 fails the multi-period lower limit check.
(See Table 12, “Multi-period Hysteresis Limits” on page 46)
R3FMU
R3FL
Reference 3 Multi-period Upper Limit Fail Bit
If the device sets this bit to high, the input REF3 fails the multi-period upper limit
check. (See Table 12, “Multi-period Hysteresis Limits” on page 46)
Reference 3 Single Period Lower Limit Fail Bit
If the device sets this bit to high, the input REF3 fails the single-period lower limit
check. (See Table 11, “Values for Single Period Limits” on page 45)
R3FU
Reference 3 Single Period Upper Limit Fail Bit
If the device sets this bit to high, the input REF3 fails the single-period upper limit
check. (See Table 11, “Values for Single Period Limits” on page 45)
R2FML
R2FMU
R2FL
Reference 2 Multi-period Lower Limit Fail Bit
If the device sets this bit to high, the input REF2 fails the multi-period lower limit check.
(See Table 12, “Multi-period Hysteresis Limits” on page 46)
Reference 2 Multi-period Upper Limit Fail Bit
If the device sets this bit to high, the input REF2 fails the multi-period upper limit
check. (See Table 12, “Multi-period Hysteresis Limits” on page 46)
Reference 2 Single Period Lower Limit Fail Bit
If the device sets this bit to high, the input REF2 fails the single-period lower limit
check. (See Table 11, “Values for Single Period Limits” on page 45)
8
R2FU
Reference 2 Single Period Upper Limit Fail Bit
If the device sets this bit to high, the input REF2 fails the single-period upper limit
check. (See Table 11, “Values for Single Period Limits” on page 45)
7
R1FML
R1FMU
R1FL
Reference 1 Multi-period Lower Limit Fail Bit
If the device sets this bit to high, the input REF1 fails the multi-period lower limit check.
(See Table 12, “Multi-period Hysteresis Limits” on page 46)
6
Reference 1 Multi-period Upper Limit Fail Bit
If the device sets this bit to high, the input REF1 fails the multi-period upper limit
check. (See Table 12, “Multi-period Hysteresis Limits” on page 46)
5
Reference 1 Single Period Lower Limit Fail Bit
If the device sets this bit to high, the input REF1 fails the single-period lower limit
check. (See Table 11, “Values for Single Period Limits” on page 45)
4
R1FU
Reference 1 Single Period Upper Limit Fail Bit
If the device sets this bit to high, the input REF1 fails the single-period upper limit
check. (See Table 11, “Values for Single Period Limits” on page 45)
Table 41 - Reference Failure Status Register (RSR) Bits - Read Only
74
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
