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ZL50022QCG1 参数 Datasheet PDF下载

ZL50022QCG1图片预览
型号: ZL50022QCG1
PDF下载: 下载PDF文件 查看货源
内容描述: 增强型4K的数字开关与地层4E DPLL [Enhanced 4 K Digital Switch with Stratum 4E DPLL]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 121 页 / 931 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50022  
Data Sheet  
External Read Only Address: 0069H  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
R3  
R3  
R3  
FL  
R3  
FU  
R2  
R2  
R2  
FL  
R2  
FU  
R1  
R1  
R1  
FL  
R1  
FU  
R0  
R0  
R0  
FL  
R0  
FU  
FML  
FMU  
FML  
FMU  
FML  
FMU  
FML  
FMU  
Bit  
Name  
Description  
3
2
1
0
R0FML  
Reference 0 Multi-period Lower Limit Fail Bit  
If the device sets this bit to high, the input REF0 fails the multi-period lower limit check.  
(See Table 12, “Multi-period Hysteresis Limits” on page 46)  
R0FMU  
R0FL  
Reference 0 Multi-period Upper Limit Fail Bit  
If the device sets this bit to high, the input REF0 fails the multi-period upper limit  
check. (See Table 12, “Multi-period Hysteresis Limits” on page 46)  
Reference 0 Single Period Lower Limit Fail Bit  
If the device sets this bit to high, the input REF0 fails the single-period lower limit  
check. (See Table 11, “Values for Single Period Limits” on page 45)  
R0FU  
Reference 0 Single Period Upper Limit Fail Bit  
If the device sets this bit to high, the input REF0 fails the single-period upper limit  
check. (See Table 11, “Values for Single Period Limits” on page 45)  
Table 41 - Reference Failure Status Register (RSR) Bits - Read Only (continued)  
External Read/Write Address: 006AH  
Reset Value: 0000H  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
R3  
R3  
R3  
ML  
R3  
R2  
R2  
R2  
ML  
R2  
R1  
R1  
R1  
ML  
R1  
R0  
R0  
R0  
ML  
R0  
MML  
MMU  
MU  
MML  
MMU  
MU  
MML  
MMU  
MU  
MML  
MMU  
MU  
Bit  
Name  
Description  
15  
14  
13  
12  
R3MML  
Reference 3 Multi-period Lower Limit Mask Bit  
When this bit is high, it masks the multi-period lower limit check (or forces pass) for  
REF3.  
R3MMU  
R3ML  
Reference 3 Multi-period Upper Limit Mask Bit  
When this bit is high, it masks the multi-period upper limit check (or forces pass) for  
REF3.  
Reference 3 Single-period Lower Limit Mask Bit  
When this bit is high, it masks the single-period lower limit check (or forces pass) for  
REF3.  
R3MU  
Reference 3 Single-period Upper Limit Mask Bit  
When this bit is high, it masks the single-period upper limit check (or forces pass) for  
REF3.  
Table 42 - Reference Mask Register (RMR) Bits  
75  
Zarlink Semiconductor Inc.  
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