ZL50022
Data Sheet
External Read/Write Address: 004BH
Reset Value: 0000H
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
6
5
4
3
2
1
0
MTR
PRS
1
PRS
0
PMS
2
PMS
1
PMS
0
FDM
1
FDM
0
Bit
Name
Description
15 - 8
Unused
Reserved
In normal functional mode, these bits MUST be set to zero.
7
MTR
MTIE Reset
When this bit is low, the MTIE circuit applies a phase offset between the reference input
clock and the DPLL output clock and the phase offset value is maintained. When this bit
is high, MTIE circuit is in its reset state and the phase offset value is reset to zero,
causing alignment of the DPLL output clocks to nearest edge of the selected input
reference.
6 - 5
PRS1 - 0 Preferred Reference Selection Bits
These bits select the preferred reference from one of the input references. They are used
only if the PMS2-0 bits are set to 001. Otherwise, these bits are ignored.
PRS1
PRS0
Preferred Reference Selection
0
0
1
1
0
1
0
1
REF0
REF1
REF2
REF3
4 - 2
PMS2 - 0 Preference Mode Selection Bits
These bits select one of the preference modes:
PMS2
PMS1
PMS0
Preference Mode
No Preference
Preference as per the setting
of the PRS1 - 0 bits
0
0
0
0
0
1
0
0
1
1
1
1
0
0
0
1
0
1
Force REF0
Force REF1
Force REF2
Force REF3
Reserved
110 - 111
If in automatic mode with a preferred reference (PMS2-0 = 001 and FDM1-0 = 00), the
automatic state machine will only switch between two references (as per Table 8). Please
see Section12.1.3.2, “Automatic Reference Switching With Preferences“ on page 41 for
more details.
Table 36 - Reference Change Control Register (RCCR) Bits
69
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
