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ZL50022QCG1 参数 Datasheet PDF下载

ZL50022QCG1图片预览
型号: ZL50022QCG1
PDF下载: 下载PDF文件 查看货源
内容描述: 增强型4K的数字开关与地层4E DPLL [Enhanced 4 K Digital Switch with Stratum 4E DPLL]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 121 页 / 931 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50022  
Data Sheet  
External Read/Write Address: 0042H  
Reset Value: 16B1H  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
CFN  
15  
CFN  
14  
CFN  
13  
CFN  
12  
CFN  
11  
CFN  
10  
CFN  
9
CFN  
8
CFN  
7
CFN  
6
CFN  
5
CFN  
4
CFN  
3
CFN  
2
CFN  
1
CFN  
0
Bit  
Name  
Description  
15 - 0  
CFN15 - 0 Center Frequency Number (CFN) Lower 16 Bits: The total binary value of these bits  
and the CFRU register bits defines the output center frequency number according to the  
following formula:  
CFN  
-----------  
fOUT =  
× fMCLK  
226  
where, fOUT is desired output center frequency, while fMCLK is frequency of DPLL master  
clock. For given master clock frequency of 100 MHz, and desired output center fre-  
quency of 65.536 MHz, the CFN has the value of:  
26  
26  
65.536MHz  
-------------------------------  
CFN = 2  
×
= 2 × 0.65536 = 43980465 = 29F16B1H  
100MHz  
The register contents should be changed only if compensation for input oscillator (or  
crystal) frequency offset is required.  
e.g., if master clock frequency is off by +20 ppm (100.002 MHz -> 5 times multiplied c20i  
of 20.0004 MHz), the CFN should be programmed to be:  
26  
26  
65.536MHz  
----------------------------------  
CFN = 2  
×
= 2 × 0.65534689 = 43979585 = 29F1341H  
100.002MHz  
The default value of this register SHOULD NOT be changed in any other circumstances.  
Table 30 - Centre Frequency Register - Lower 16 Bits (CFRL)  
External Read/Write Address: 0043H  
Reset Value: 029FH  
15  
0
14  
0
13  
0
12  
0
11  
0
10  
0
9
8
7
6
5
4
3
2
1
0
CFN  
25  
CFN  
24  
CFN  
23  
CFN  
22  
CFN  
21  
CFN  
20  
CFN  
19  
CFN  
18  
CFN  
17  
CFN  
16  
Bit  
Name  
Description  
Reserved. In normal functional mode, these bits MUST be set to zero.  
15 - 10  
9 - 0  
Unused  
CFN25 - 16 Center Frequency Number (CFN) Upper 10 Bits: The total binary value of these bits  
and the CFRL register bits represents the center frequency number (CFN) explained  
under CFRL register bits explanation.  
The default value of this register should be changed only if compensation for input oscil-  
lator (or crystal) frequency offset is required, and SHOULD NOT be changed in any other  
circumstances.  
Table 31 - Centre Frequency Register - Upper 10 Bits (CFRU)  
66  
Zarlink Semiconductor Inc.  
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