ZL50022
Data Sheet
tFPW2
VCT
FPo2/FPo3
CKo2/CKo3
tFODF2
tFODR2
tCKP2
tCKH2
tCKL2
VCT
trCK2
tfCK2
Output Frame Boundary
Figure 44 - FPo2 and CKo2 or FPo3 and CKo3 (16.384 MHz) Timing Diagram
AC Electrical Characteristics† - FPo2 and CKo2 or FPo3 and CKo3 (16.384 MHz) Timing (Master Mode, Divided Slave Mode, or
Multiplied Slave Mode with less than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic
FPo2 Output Pulse Width
FPo2 Output Delay from the FPo2 falling edge
to the output frame boundary
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
tFPW2
tFODF2
56
25
61
66
36
ns
ns
CL = 30 pF
3
FPo2 Output Delay from the output frame
boundary to the FPo2 rising edge
tFODR2
25
36
ns
4
5
6
7
CKo2 Output Clock Period
CKo2 Output High Time
CKo2 Output Low Time
CKo2 Output Rise/Fall Time
tCKP2
tCKH2
tCKL2
56
25
25
61
66
36
36
5
ns
ns
ns
ns
CL = 30 pF
t
rCK2, tfCK2
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPo2 and CKo2 or FPo3 and CKo3 (16.384 MHz) Timing (Multiplied Slave Mode with more than
10 ns of Cycle to Cycle Variation on CKi)
Characteristic
FPo2 Output Pulse Width
FPo2 Output Delay from the FPo2 falling edge
to the output frame boundary
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
tFPW2
tFODF2
56
25
61
66
36
ns
ns
CL = 30 pF
3
FPo2 Output Delay from the output frame
boundary to the FPo2 rising edge
tFODR2
25
36
ns
4
5
6
7
CKo2 Output Clock Period
CKo2 Output High Time
CKo2 Output Low Time
CKo2 Output Rise/Fall Time
tCKP2
tCKH2
tCKL2
47
17
17
61
76
43
43
5
ns
ns
ns
ns
CL = 30 pF
t
rCK2, tfCK2
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
110
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
