ZL50022
Data Sheet
tFPW5
FPo5
(shares output pin
with FPo_OFF2)
VCT
tFODF5
tFODR5
tCKP5
tCKH5
tCKL5
VCT
CKo5
trCK5
tfCK5
Output Frame Boundary
Figure 47 - CKo5 Timing Diagram (19.44 MHz)
AC Electrical Characteristics† - CKo5 (19.44 MHz) Timing (Only when DPLL is active)
Characteristic
FPo5 Output Pulse Width
FPo5 Output Delay from the FPo5 falling edge
to the output frame boundary
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
tFPW5
tFODF5
49
22
51
25
55
28
ns
ns
CL = 30 pF
3
FPo5 Output Delay from the output frame
boundary to the FPo5 rising edge
tFODR5
21
25
32
ns
4
5
6
7
CKo5 Output Clock Period
CKo5 Output High Time
CKo5 Output Low Time
CKo5 Output Rise/Fall Time
tCKP5
tCKH5
tCKL5
50
23
24
51
25
25
53
27
28
5
ns
ns
ns
ns
t
rCK5, tfCK5
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
113
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
