ZL50022
Data Sheet
tFPW3
VCT
FPo3
CKo3
tFODF3
tFODR3
tCKP3
tCKH3
tCKL3
VCT
trCK3
tfCK3
Output Frame Boundary
Figure 45 - FPo3 and CKo3 (32.768 MHz) Timing Diagram
AC Electrical Characteristics† - FPo3 and CKo3 (32.768 MHz) Timing (Master Mode, Divided Slave Mode, or Multiplied Slave
Mode with less than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic
FPo3 Output Pulse Width
FPo3 Output Delay from the FPo3 falling edge
to the output frame boundary
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
tFPW3
tFODF3
27
10
30.5
34
18
ns
ns
CL = 30 pF
3
FPo3 Output Delay from the output frame
boundary to the FPo3 rising edge
tFODR3
12
21
ns
4
5
6
7
CKo3 Output Clock Period
CKo3 Output High Time
CKo3 Output Low Time
CKo3 Output Rise/Fall Time
tCKP3
tCKH3
tCKL3
27
12
12
30.5
34
19
19
5
ns
ns
ns
ns
CL = 30 pF
trCK3, tfCK3
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPo3 and CKo3 (32.768 MHz) Timing (Multiplied Slave Mode with more than 10 ns of Cycle to
Cycle Variation on CKi
Characteristic
FPo3 Output Pulse Width
FPo3 Output Delay from the FPo3 falling edge
to the output frame boundary
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
tFPW3
tFODF3
27
12
30.5
34
19
ns
ns
CL = 30 pF
3
FPo3 Output Delay from the output frame
boundary to the FPo3 rising edge
tFODR3
12
19
ns
4
5
6
7
CKo3 Output Clock Period
CKo3 Output High Time
CKo3 Output Low Time
CKo3 Output Rise/Fall Time
tCKP3
tCKH3
tCKL3
17
5
12
30.5
44
29
18
5
ns
ns
ns
ns
CL = 30 pF
t
rCK3, tfCK3
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
111
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
