ZL50022
Data Sheet
tFPW1
VCT
FPo1/FPo3
CKo1/CKo3
tFODF1
tFODR1
tCKP1
tCKH1
tCKL1
VCT
trCK1
tfCK1
Output Frame Boundary
Figure 43 - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing Diagram
AC Electrical Characteristics† - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing (Master Mode, Divided Slave Mode, or
Multiplied Slave Mode with less than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic
FPo1 Output Pulse Width
FPo1 Output Delay from the FPo1 falling edge
to the output frame boundary
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
tFPW1
tFODF1
117
56
122
127
66
ns
ns
CL = 30 pF
3
FPo1 Output Delay from the output frame
boundary to the FPo1 rising edge
tFODR1
56
66
ns
4
5
6
7
CKo1 Output Clock Period
CKo1 Output High Time
CKo1 Output Low Time
CKo1 Output Rise/Fall Time
tCKP1
tCKH1
tCKL1
117
56
56
122
127
66
66
5
ns
ns
ns
ns
CL = 30 pF
t
rCK1, tfCK1
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing (Multiplied Slave Mode with more than
10 ns of Cycle to Cycle Variation on CKi)
Characteristic
FPo1 Output Pulse Width
FPo1 Output Delay from the FPo1 falling edge
to the output frame boundary
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
tFPW1
tFODF1
106
56
122
127
66
ns
ns
CL = 30 pF
3
FPo1 Output Delay from the output frame
boundary to the FPo1 rising edge
tFODR1
46
66
ns
4
5
6
7
CKo1 Output Clock Period
CKo1 Output High Time
CKo1 Output Low Time
CKo1 Output Rise/Fall Time
tCKP1
tCKH1
tCKL1
106
46
46
122
148
87
66
5
ns
ns
ns
ns
CL = 30 pF
t
rCK1, tfCK1
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
109
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
