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ZL50022QCG1 参数 Datasheet PDF下载

ZL50022QCG1图片预览
型号: ZL50022QCG1
PDF下载: 下载PDF文件 查看货源
内容描述: 增强型4K的数字开关与地层4E DPLL [Enhanced 4 K Digital Switch with Stratum 4E DPLL]
分类和应用: 开关电信集成电路电信转换电路电信电路
文件页数/大小: 121 页 / 931 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL50022  
Data Sheet  
FPo0  
CKo4  
VCT  
tCKP4  
tCKH4  
tCKL4  
VCT  
trCK4  
tfCK4  
Output Frame Boundary  
Figure 46 - FPo4 and CKo4 Timing Diagram (1.544/2.048 MHz)  
AC Electrical Characteristics- CKo4 (1.544 MHz) Timing (Only when DPLL is active)  
Characteristic  
CKo4 Output Clock Period  
CKo4 Output High Time  
CKo4 Output Low Time  
CKo4 Output Rise/Fall Time  
Sym.  
Min. Typ.Max. Units  
Notes  
1
2
3
4
tCKP4  
tCKH4  
tCKL4  
645  
320  
320  
648  
324  
324  
650  
327  
327  
5
ns  
ns  
ns  
ns  
CL = 30 pF  
t
rCK4, tfCK4  
† Characteristics are over recommended operating conditions unless otherwise stated.  
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.  
AC Electrical Characteristics- CKo4 (2.048 MHz) Timing (Only when DPLL is active)  
Characteristic  
Sym.  
Min. Typ.Max. Units  
Notes  
1
2
3
4
CKo4 Output Clock Period  
tCKP4  
tCKH4  
tCKL4  
485  
241  
241  
488  
244  
244  
492  
247  
247  
5
ns  
ns  
ns  
ns  
CL = 30 pF  
CKo4 Output High Time  
CKo4 Output Low Time  
CKo4 Output Rise/Fall Time  
t
rCK4, tfCK4  
† Characteristics are over recommended operating conditions unless otherwise stated.  
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.  
112  
Zarlink Semiconductor Inc.  
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