ZL50022
Data Sheet
tFPW0
VCT
FPo0/FPo3
CKo0/CKo3
tFODF0
tFODR0
tCKP0
tCKH0
tCKL0
VCT
trCK0
tfCK0
Output Frame Boundary
Figure 42 - FPo0 and CKo0 or FPo3 and CKo3 (4.096 MHz) Timing Diagram
AC Electrical Characteristics† - FPo0 and CKo0 or FPo3 and CKo3 (4.096 MHz) Timing (Master Mode, Divided Slave Mode, or
Multiplied Slave Mode with less than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic
FPo0 Output Pulse Width
FPo0 Output Delay from the FPo0 falling edge
to the output frame boundary
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
tFPW0
tFODF0
239
117
244
249
127
ns
ns
CL = 30 pF
3
FPo0 Output Delay from the output frame
boundary to the FPo0 rising edge
tFODR0
117
127
ns
4
5
6
7
CKo0 Output Clock Period
CKo0 Output High Time
CKo0 Output Low Time
CKo0 Output Rise/Fall Time
tCKP0
tCKH0
tCKL0
239
117
117
244
249
127
127
5
ns
ns
ns
ns
CL = 30 pF
t
rCK0, tfCK0
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPo0 and CKo0 or FPo3 and CKo3 (4.096 MHz) Timing (Multiplied Slave Mode with more than
10 ns of Cycle to Cycle Variation on CKi)
Characteristic
FPo0 Output Pulse Width
FPo0 Output Delay from the FPo0 falling edge
to the output frame boundary
Sym.
Min. Typ.‡ Max. Units
Notes
1
2
tFPW0
tFODF0
218
117
244
270
127
ns
ns
CL = 30 pF
3
FPo0 Output Delay from the output frame
boundary to the FPo0 rising edge
tFODR0
97
146
ns
4
5
6
7
CKo0 Output Clock Period
CKo0 Output High Time
CKo0 Output Low Time
CKo0 Output Rise/Fall Time
tCKP0
tCKH0
tCKL0
218
117
97
244
270
127
146
5
ns
ns
ns
ns
CL = 30 pF
t
rCK0, tfCK0
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
108
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
