ZL30402
Data Sheet
4.2.2 Status Bits
The ZL30402 has seven status bits (see Figure 6 "Hardware and Software Control options"). The first two bits
perform the same function as their equivalent status pins. The last five bits perform two functions. Bits FLIM, PAFL,
SAFL indicate drift of the reference clock frequencies beyond the capture range of Acquisition and Core PLLs and
bits PAH and SAH show entry of Primary and Secondary Acquisition PLLs into Holdover mode. These bits are
described in detail in section 3.2.4. The status pins are enabled when the ZL30402 operates in software control and
they can be used to trigger interrupts.
4.2.3 ZL30402 Register Map
Addresses: 00H to 6FH
Address
hex
Read
Write
R/W
R
Register
Control Register 1
Function
00
01
04
06
07
RefSel, 0, 0, MS2, MS1, FCS, 0, RefAlign
rsv, rsv, LOCK, HOLDOVER, rsv, FLIM, rsv, rsv
E3DS3/OC3, E3/DS3, 0, 0, 0, 0, 0, 0,
Status Register 1
Control Register 2
R/W
R/W
R/W
Phase Offset Register 2
Phase Offset Register 1
0, 0, 0, 0, OffEn, C16POA10, C16POA9, C16POA8
C16POA7, C16POA6, C16POA5, C16POA4, C16POA3,
C16POA2, C16POA1, C16POA0
0F
11
13
14
19
1A
Device ID Register
R
0010 0001
Control Register 3
R/W
R/W
R/W
R/W
R/W
rsv, rsv, C1.5POA2, C1.5POA1, C1.5POA0, 0, 0, 0
0, 0, C16dis, C8dis, C4dis, C2dis, C1.5dis,0
0, 0, 0, F8odis, F0odis, F16odis, C6dis, C19dis
0, 0, 0, 0, 0, 0, MHR, AHRD, 0
Clock Disable Register 1
Clock Disable Register 2
Core PLL Control Register
Fine Phase Offset Register
FPOA7, FPOA6, FPOA5, FPOA4, FPOA3, FPOA2, FPOA1,
FPOA0
20
28
40
Primary Acquisition PLL Status
Register
R
R
rsv, rsv, rsv, rsv, InpFreq1, InpFreq0, rsv, PAH,PAFL
Secondary Acquisition PLL
rsv, rsv, rsv, rsv, InpFreq1, InpFreq0, rsv, SAH, SAFL
Status Register
Master Clock Frequency
R/W
MCFC31, MCFC30, MCFC29, MCFC28, MCFC27, MCFC26,
MCFC25, MCFC24,
Calibration Register - Byte 4
41
42
43
Master Clock Frequency
R/W
R/W
R/W
MCFC23, MCFC22, MCFC21, MCFC20, MCFC19, MCFC18,
MCFC17, MCFC16
Calibration Register - Byte 3
Master Clock Frequency
MCFC15, MCFC14, MCFC13, MCFC12, MCFC11, MCFC10,
MCFC9, MCFC8
Calibration Register - Byte 2
Master Clock Frequency
MCFC7, MCFC6, MCFC5, MCFC4, MCFC3, MCFC2, MCFC1,
MCFC0
Calibration Register - Byte 1
Table 4 - ZL30402 Register Map
Note: The ZL30402 uses address space from 00h to 6Fh. Registers at address locations not listed above must not be written or read.
20
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
