ZL30402
Data Sheet
4.2.4 Register Description
Address: 00 H
Bit
Name
Functional Description
Default
7
RefSel
0
Reference Select. A zero selects the PRI (Primary) reference source
as the input reference signal and a one selects the SEC (secondary)
reference.
6-5
4-3
RSV
00
10
Reserved.
MS2, MS1
Mode Select
- MS2 = 0 MS1 = 0 Normal Mode (Locked Mode)
- MS2 = 0 MS1 = 1 Holdover Mode
- MS2 = 1 MS1 = 0 Free-run Mode
- MS2 = 1 MS1 = 1 Reserved
2
FCS
0
Filter Characteristic Select
FCS = 0 Filter corner frequency set to 1.1 Hz. This selection meets
requirements of G.813 Option 1 and GR-1244 stratum 3 clocks.
FCS = 1 Filter corner frequency set to 0.1 Hz. This selection meets
requirements of G.813 Option 2, GR-253 for SONET stratum 3 and
GR-253 for SONET Minimum Clocks (SMC).
1
0
RSV
0
1
Reserved.
RefAlign
Reference Align. A high-to-low transition aligns the generated output
clocks to the input reference signal. The maximum phase slope
depends on the Filter Characteristic selected and is limited to:
- 41ns in 1.326ms for FCS = 0
- 885 ns in 1s for FCS = 1
Table 5 - Control Register 1 (R/W)
21
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
