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ZL30402/QCC 参数 Datasheet PDF下载

ZL30402/QCC图片预览
型号: ZL30402/QCC
PDF下载: 下载PDF文件 查看货源
内容描述: SONET / SDH网元PLL [SONET/SDH Network Element PLL]
分类和应用: 电信集成电路异步传输模式ATM
文件页数/大小: 44 页 / 471 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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ZL30402  
Data Sheet  
Pin Description  
Pin #  
Name  
Description  
Internal Connection. Leave unconnected.  
1
IC  
2-5  
A1-A4  
Address 1 to 4 (5 V tolerant input). Address inputs for the parallel processor  
interface. Connect to ground in Hardware Control.  
6
GND  
Ground. Negative power supply.  
7-8  
A5-A6  
Address 5 to 6 (5 V tolerant input). Address inputs for the parallel processor  
interface. Connect to ground in Hardware Control.  
9
FCS  
Filter Characteristic Select (Input). In Hardware Control, FCS selects the  
filtering characteristics of the ZL30402. Set this pin high to have a loop filter  
corner frequency of 0.1 Hz and limit the phase slope to 885 ns per second. Set  
this pin low to have corner frequency of 1.1 Hz and limit the phase slope to  
41 ns per 1.326 ms. Connect to ground in Software Control. This pin is  
internally pulled down to GND.  
10  
11  
12  
VDD  
GND  
F16o  
Positive Power Supply.  
Ground.  
Frame Pulse ST-BUS 8.192 Mb/s (CMOS tristate output). This is an 8 kHz,  
61 ns wide, active low framing pulse, which marks beginning of a ST-BUS  
frame. This frame pulse is typically used for ST-BUS operation at 8.192 Mb/s  
13  
14  
15  
16  
17  
C16o  
C8o  
C4o  
C2o  
F0o  
Clock 16.384 MHz (CMOS tristate output). This clock is used for ST-BUS  
operation at 8.192 Mb/s.  
Clock 8.192 MHz (CMOS tristate output). This clock is used for ST-BUS  
operation at 8.192 Mb/s.  
Clock 4.096 MHz (CMOS tristate output). This clock is used for ST-BUS  
operation at 2.048 Mb/s.  
Clock 2.048 MHz (CMOS tristate output). This clock is used for ST-BUS  
operation at 2.048 Mb/s.  
Frame Pulse ST-BUS 2.048 Mb/s (CMOS tristate output). This is an 8 kHz,  
244 ns, active low framing pulse, which marks the beginning of a ST-BUS  
frame. This is typically used for ST-BUS operation at 2.048 Mb/s and  
4.096 Mb/s.  
18  
19  
MS1  
MS2  
Mode Select 1 (Input). The MS1 and MS2 pins select the ZL30402 mode of  
operation (Normal, Holdover or Free-run), see Table 1 on page 18 for details.  
The logic level at this input is sampled by the rising edge of the F8o frame  
pulse. Connect to ground in Software Control.  
Mode Select 2 (Input). The MS2 and MS1 pins select the ZL30402 mode of  
operation (Normal, Holdover or Free-run), see Table 1 on page 18 for details.  
The logic level at this input is sampled by the rising edge of the F8o frame  
pulse. Connect to ground in Software Control.  
7
Zarlink Semiconductor Inc.