MT90826
Data Sheet
6.0 Memory Mapping
The address bus on the microprocessor interface selects the internal registers and memories of the MT90826. If
the A13 address input is low, then the registers are addressed by A12 to A0 according to Table 3.
If the A13 is high, the remaining address input lines are used to select location in the data or connection memory
depending upon MS bit in the control register. For data memory reads, the serial inputs are selected. For
connection memory writes, the serial outputs are selected. The destination stream address bits and channel
address bits are defined by A12 to A8 and A7 to A0 respectively. See Table 4 for the memory address mapping.
The control register controls all the major functions of the device. It selects the internal memory locations that
specify the input and output channels selected for switching and should be programmed immediately after system
power-up to establish the desired switching configuration as explained in the Switching Configurations sections.
The data in the control register consists of the block programming (BPD0-2), the DPLL control (CPLL), the clear
BER test (CBER), the start BER test (SBER), the start frame evaluation (SFE), the block programming enable
(BPE), the memory block programming bit (MBP), the memory select bits (MS), the output stand by bit (OSB) and
the data rate selection (DR0-2) bits. See Table 5 for the description of the control register bits.
7.0 Connection Memory Control
The connection memory controls the switching configuration of the device. Locations of the connection memory are
associated with particular STo output streams.
The TM0 and TM1 bits of each connection memory location allows the selection of Variable throughput delay,
Constant throughput delay, Message or Bit error test mode for all STo channels.
When the variable or constant throughput delay mode is selected, (TM1=0/1, TM0=0), the contents of the stream
address bit (SAB) and the channel address bit (CAB) of the connection memory defines the source information
(stream and channel) of the timeslot that will be switched to the STo streams.
When the message mode is selected, (TM1=0, TM0=1) , only the lower half byte (8 least significant bits) of the
connection memory is transferred to the associated STo output channel.
When the bit error test mode is selected, (TM1=1, TM0=1), the pseudo random pattern will be output on the
associated STo output channel.
See Table 14 for the description of the connection memory bits.
8.0 DTA Data Transfer Acknowledgment Pin
The DTA pin is driven LOW by internal logic, to indicate to the CPU that a data bus transfer is complete. When the
read or write cycle ends, this pin changes to the high-impedance state.
29
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
