MT312 Electrical Characteristics
Pin
Name
Description
I/O
Note
V
mA
1
53
24
CLK1
2-wire serial bus clock
I
CMOS
5
ADCFGND ADC core front end VSS. Must be
connected to analogue GND.
0
0
22
PLLGND
PLL VSS. Must be connected to
analogue GND.
77,78,79,80,3
IIN[5:1]
Test bus, all inputs must be connected to
VSS.
I/O
CMOS
3.3
1
Note 1. 8V tolerant pins with thresholds related to 3.3V.
12.6 Alphabetical Listing of Pin-Out
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
PIN
ADCAGND
ADCAVDD
ADCDVDD
ADCDGND
ADCFGND
ADCFVDD
ADDR[1]
ADDR[2]
ADDR[3]
ADDR[4]
ADDR[5]
ADDR[6]
ADDR[7]
AGC
36
37
30
31
24
25
12
11
8
CVDD
CVDD
17
42
50
62
67
1
IIN[4]
IIN[5]
78
77
27
57
28
59
61
63
64
65
66
68
69
71
14
PLLVDD
QREF
QSINGP
RESET
RREF
STATUS
TEST1
TEST2
TESTCLK
VRB
21
34
33
49
38
52
39
40
16
35
32
26
13
55
73
CVDD
IREF
CVDD
IRQ
CVDD
ISINGP
MDO[0]
MDO[1]
MDO[2]
MDO[3]
MDO[4]
MDO[5]
MDO[6]
MDO[7]
MDOEN
MICLK
CVSS
CVSS
10
20
41
51
60
70
54
45
48
CVSS
CVSS
7
CVSS
6
CVSS
VRM
5
CVSS
VRT
4
DATA1
DATA2/GPP1
VDD
43
75
CVDD
VDD
BKERR
DISEQC0
22kHz
CLK1
53
44
DISEQC1 HV
47
46
MOCLK
58
76
VSS
VSS
15
56
CLK2/GPP0
DISEQC2/
GPP2
MOSTRT
NC
29
2
IIN[1]
IIN[2]
IIN[3]
3
MOVAL
PLL1
72
23
22
VSS
XTI
74
18
19
CVDD
CVDD
80
79
9
PLLGND
XTO
Table 12 - Alphabetical listing of pin-out
82
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
