Register Map MT312
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
Page
DISEQC2
CTRL2
122
MIN PULS PER
TONE EXT PER
MAX TONE PER
R/W
R/W
D4
32
CONFIG
127
312 EN
DSS B
DSS A
BPSK
PLL FACTOR[1:0]
CRYS15
ADC
EXT
08
22
14.2 Read Only Register Map
Writing to these registers will have no effect
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
Page
QPSK INT H
QPSK INT M
QPSK INT L
FEC INT
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
108
109
110
QPSK INT[23:16] Interrupt QPSK (high byte)
QPSK INT [15:8] Interrupt QPSK (middle byte)
QPSK INT [7:0] Interrupt QPSK (low byte)
FEC INT[7:0] Interrupt FEC
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
42
42
42
48
44
44
49
27
27
49
49
50
50
50
50
50
50
51
51
53
85
85
85
28
28
28
28
28
44
44
33
QPSK STAT H
QPSK STAT L
FEC STATUS
LNB FREQ H
LNB FREQ L
M SNR H
QPSK STATUS[15:8] (high byte)
QPSK STATUS[7:0] (low byte)
FEC STATUS[7:0]
LNB FREQ[15:8] Measured LNB frequency error (high byte)
LNB FREQ [7:0] Measured LNB frequency error (low byte)
M SNR[14:8] Measured SNR (high byte)
Reserved
M SNR L
M SNR [7:0] Measured SNR (low byte)
VIT ERRCNT H
VIT ERRCNT M
VIT ERRCNT L
RS BERCNT H
RS BERCNT M
RS BERCNT L
RS UBC H
VIT ERRCNT[23:16] - Viterbi error count (high byte)
VIT ERRCNT[15:8] - Viterbi error count (middle byte)
VIT ERRCNT[7:0] - Viterbi error count (low byte)
RS BERCNT[23:16] - Reed Solomon bit errors corrected (high byte)
RS BERCNT[15:8] - Reed Solomon bit errors corrected (middle byte)
RS BERCNT[7:0] - Reed Solomon bit errors corrected (low byte)
RS UBC[15:8] - Reed Solomon uncorrected block errors (high byte)
RS UBC[7:0] - Reed Solomon uncorrected block errors (low byte)
SIG LEVEL[11:4] - Signal level at MT312 input
RS UBC L
SIG LEVEL
AGC H
AGC (23:16] - Front end AGC (high byte)
AGC M
AGC[15:8] - Front end AGC (middle byte)
AGC L
AGC[7:0] - Front end AGC (low byte)
FREQ ERR1 H 111
FREQ ERR1 M 112
FREQ ERR1[23:16] Input frequency error course (high byte)
FREQ ERR1[15:8] Input frequency error course (middle byte)
FREQ ERR1[7:0] Input frequency error course (low byte)
FREQ ERR2[15:8] Input frequency error fine (high byte)
FREQ ERR2[7:0] Input frequency error fine (low byte)
SYM RAT OP[15:8] Symbol Rate Output (high byte)
SYM RAT OP[7:0] Symbol Rate Output (low byte)
DISEQC2 INT[7:0]
FREQ ERR1 L
FREQ ERR2 H 114
FREQ ERR2 L 115
113
SYM RAT OP H 116
SYM RAT OP L 117
DISEQC2 INT
118
85
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
