MT312 Register Map
14 MT312 Register Map
RADD is a virtual register with no address containing the address of the register to be accessed. It is written
immediately after the 2-wire write address.
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
RADD
N/A
IAI
AD6
AD5
AD4
AD3
AD2
AD1
AD0
W
-
14.1 Read / Write Register Map
Def
hex
NAME
ADR
B7
B6
B5
B4
B3
B2
B1
B0
Page
GPP CTRL
RESET
20
21
22
23
24
25
26
Reserved 2W PAS
GPP DIR[2:0]
PR QP
GPP PIN[2:0]
PR BA
R/W
20
00
00
1B
80
44
00
25
21
30
36
36
38
39
FR 312
PR 312
HV
FR QP
FR VIT
PR VIT
PR DS R/W
R/W
DISEQC MODE
SYM RATE H
SYM RATE L
VIT MODE
Reserved
DISEQC instruction length
22kHz mode
SEARCH Reserved
SYM RATE[13:8] in MBaud )high byte)
SYM RATE[7:0] in MBaud (low byte)
CR 7/8 CR 6/7 CR 5/6 CR 3/4
R/W
R/W
AUT IQ
V IQ SP
CR 2/3
CR 1/2 R/W
QPSK CTRL
Reserved Q IQ SP Reserved Reserved Reserved AFC M Reserved ROLL R/W
20
GO
27
28
29
30
31
32
33
Reserved
GO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00
00
00
00
00
00
14
40
40
40
40
47
41
47
IE QPSK H
IE QPSK M
IE QPSK L
IE FEC
IE QPSK[23:16] Interrupt enable QPSK (high byte)
IE QPSK[15:8] Interrupt enable QPSK (middle byte)
IE QPSK[7:0] Interrupt enable QPSK (low byte)
IE FEC[7:0] Interrupt enable FEC
QPSK STAT EN
FEC STAT EN
QPSK STAT EN[7:0] Enable various QPSK outputs on STATUS pin
MOCLK RATIO[3:0]
DS Lock BA lock VIT lock
BER
tog
SYS CLK
DISEQC RATIO
DISEQC INSTR
FR LIM
34
35
36
37
38
39
SYS CLK[7:0] - System clock frequency x2 in MHz
R/W
R/W
R/W
R/W
R/W
R/W
00
00
00
00
00
26
23
30
31
26
27
52
DISEQC RATIO[7:0]
DISEQC Instruction[7:0]
Reserved
FR LIM[6:0] - Freq. Limit in MHz
FR OFF[7:0] - Freq. Offset in MHz
FR OFF
AGC CTRL
Reserved Reserved
AGC SD[1:0]
AGC BW[2:0]
AGC
SL
AGC REF
OP CTRL
41
96
AGC REF[7:0] AGC reference level
R/W
R/W
67
03
52
59
MANUAL BKERIV MCLKINV
MOCLK
EN TEI
BSO
BA LK[2:0]
FEC SETUP
97
DIS SR
ENCLKO
DIS DS
DIS RS
DIS VIT
EN
PRS
DS LK[1:0]
R/W
00
48
MON CTRL
103 ERR IND
121
Reserved
MON CTRL[3:0] Monitor control
R/W
R/W
00
00
59
31
DISEQC2
CTRL1
DISEQC2 CTRL1[7:8]
84
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