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MT312C 参数 Datasheet PDF下载

MT312C图片预览
型号: MT312C
PDF下载: 下载PDF文件 查看货源
内容描述: 卫星频道解码器 [Satellite Channel Decoder]
分类和应用: 解码器
文件页数/大小: 90 页 / 315 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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Initialisation MT312  
3.4 Spectral Inversion  
If no spectral inversion is caused by the receiver  
front-end design, then bit B6 of QPSK CTRL must  
always be held at zero. If the transmitted signal is  
known to be spectrally inverted, then V IQ SP bit B6  
of the VIT MODE register (25) must be set to 1. Then  
I and Q are swapped after QPSK demodulation. If  
the spectral inversion status of the transmitted signal  
is not known, then after QPSK has locked (i.e. QPSK  
CT LOCK = 1), the software must try to achieve FEC  
lock with the bit B6 of VIT MODE register rst at zero  
and then at one.  
Spectral inversion of the QPSK signal can be caused  
by the transmitter or the receiver front-end. In the  
latter case, this could happen due to the way I-Q  
conversion is carried out or because the I and Q  
wires are swapped between the I-Q converter and  
the MT312. If spectral inversion is caused by the  
receiver front-end, then this must be removed by  
swapping I and Q (within MT312) before QPSK  
demodulation, by setting Q IQ SP bit B6 of QPSK  
CTRL register (26) to 1.  
3.5 MT312 Initialisation Read/Write Registers  
3.5.1 Reset. Register 21 (R/W)  
Def  
hex  
NAME  
ADR  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
RESET  
21  
FR  
312  
PR  
312  
FR  
QP  
PR  
QP  
FR  
VIT  
PR  
VIT  
PR  
BA  
PR  
DS  
R/W  
00  
B7:  
B6:  
B5:  
B4:  
B3:  
B2:  
B1:  
B0:  
FR 312  
High = Full reset of MT312 device.  
High = Partial reset of MT312 device.  
High = Full reset of QPSK block.  
High = Partial reset of QPSK block.  
High = Full reset of Viterbi block.  
High = Partial reset of Viterbi block.  
High = Partial reset of Byte Align block.  
PR 312  
FR QP  
PR QP  
FR VIT  
PR VIT  
PR BA  
PR DS  
High = Partial reset of De-scrambler block.  
Writing a one to these register locations generates a reset pulse three crystal clock periods wide.  
The register automatically resets to zero after use.  
A full reset does reset the registers to their default values.  
A partial reset does not reset the registers to their default values.  
21  
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