MA28138
Note: For all bus selections, DMAKn must be granted to the
DMA controller so that the required DMA exchange can be
completed before the next data word is placed into or removed
from its buffer in order to prevent a DMA Overrun condition
occurring. For II, IR and OR mode transfers, this period is
controlled by the CTU and may be lengthened to suit expected
DMA availability.
Additionally, in OB mode, if DMA access cannot be
obtained, data transmission to the BT-bus is simply inhibited
(and delayed) until such access can be obtained and no DMA
error is generated. This mechanism permits the OB mode
output transmission rate to the BT-bus to adapt to DMA
availability. Similarly, in the IB mode, data words which are
missing from the BT-bus data stream will not be transferred to
the RBl’s DMA controller and will not hence change the
address and length registers.
Validity, parity or length errors on the OBDH Interrogation
bus will cause the affected Interrogation to be ignored. Mode 7
‘Proceed’ instructions ignored in this way will result in underrun
- one (or more) data word(s) will be missing from the
transferred data block. For II and OR mode transfers, there will
also be no response. For OB mode transfers, there will be no
BT bus activity. In all modes, underrun may be detected by
sending Mode 0 ‘Read Address’ and ‘Read Length’ commands
and comparing the values obtained with those expected. For
IR and IB mode transfers, the CTU is also able to conduct
similar checks during the transfer process.
Note that either the DMA Overrun or DMA Error conditions
will cause the TFRERR output pin to be raised until either a
Read Status or a DMA Reset command is received. While
TFRERR is high, no DMA data transfers will be permitted and
no responses to Mode 7 Proceed commands will be
generated.
NORMAL OPERATION
1. POWER UP
Power up resets the RBI, so the CTU must set up the RBI
bus selection and direction, (and UCC, PA if required), DMA
address and length before proceeding with the first transfer.
2. DMA ENABLE
The user processor must allow RBI direct memory access
(DMA) during data transfers. The CTU can read the processor
DMA Enable (DMAE) status via a BIL user input pin and, if
necessary, send a UCC interrupt to ensure that DMA is
enabled before the transfer is begun. RBI failstops if the user
disables DMA during transfer.
3. HANDSHAKING
The OBDH and RBI protocols were designed for
handshaking. For error-free operation, the CTU may check
each response before sending the next instruction.
4. TYPICAL TRANSFER INSTRUCTION SEQUENCE
CTU instructions ‘single-step’ the RBI down a transfer
sequence e.g. that shown in Figure 9. Additionally, the CTU
may wish to check that each data block has been successfully
transferred. For II mode transfers, check for a zero length
response to the final ‘Proceed’ command; for all other modes,
perform a ‘Read Length’ instruction and perform a similar
check. Additionally, for all bus selections, perform a ‘Read
Status’ instruction and inspect the response for DMA error or
DMA overrun indications in bits 4-6.
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