MA28138
RBI TIMING
Bit Position
RIRSYNC
RIRCLK
1
RIRDATA
RIRVAL
BCP(1:4)
BCPVAL
Bit Position
RIRSYNC
RIRCLK
RIRDATA
RIRVAL
BCP(1:4)
BCPVAL
1
= BCP(4) or TA(0)
Note 1: Bit 6 of the Interrogation will be interpreted as BCP(4) if (EXTFMT = 0);
if (EXTFMT = 1), the BCP (4) output will be 0 and bit 6 will be interpreted as TA(0).
Note 2: (RIRVAL = 0) (presumably because of bad Interrogation length or received Litton coding errors detected by the
modem), bad received parity in bit 31 of the Interrogation or wrong Interrogation length will both cause the
Interrogation to be rejected and will set BCPVAL = 0.
Figure 10: BroadCast Pulse and BCP Validity Waveforms
Figures 11 and 12 show ‘slot’-level activity to be expected
on the OnBoard Data Handling Bus DBI interface. The timing
resolution shown for control signals is also shown at the ‘slot’
level for convenience; for more detail see Figures 13 to 18.
The exact timing of DMA operations and control signals
associated with them will depend upon response to the DMA
Request (DMARn) signal by external circuitry (typically a
microprocessor or a DMA Arbiter) and the resulting timing of
the associated DMA Acknowledge (DMAKn) signal.
Note that RBI operation in general is determined by more
than one clock signal - RIRCLK, RRRCLK and RBRCLK clock
edges used to capture and generate all signals on the DBI
interface and OSC clock edges used to determine the timing of
all signals on the CPU interface.
12
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
