MA28138
4. MODE 4 (LOAD BLOCK LENGTH)
RBI ARCHITECTURE
Mode 4 interrogations load the RBl’s DMA Block Length
register. In input modes, the associated response contains the
RBl’s new block length provided that no data transfers have
taken place (using the ‘Proceed’ command) before it is
transmitted. In output modes, the new block length indicated in
the response will normally have been decremented since the
RBl’s DMA controller will have performed the first fetch from
the CPU’s memory. This command cannot be omitted. A value
of 0 in the length register inhibits any transfer and sets the
“DMA Overrun” flag in the RBI status register if a transfer is
attempted.
The MA28138 OBDH RBI basically acts as a DMA
controller connected to the user’s memory which is controlled
from the OBDH bus. It contains five major components: an
Interrogation Decoder and Sequencer, a Response Generator
and Decoder, a Block Transfer Generator and Decoder, a
single-bit Broadcast Poll Generator and the DMA Controller.
All data exchange with the user is accomplished in blocks
using the DMA controller, but the OBDH bus used to carry the
data can be selected by the CTU using appropriate set-up
commands. The optional Block Transfer bus is fully supported.
The user’s status can be inspected from the CTU via a 6-bit
dedicated parallel input port (BIL(0:5)). Similarly, interrupts,
hardware run/stop/halt signals, etc. can be delivered to a 7-bit
dedicated parallel output port (UCC(0:6)). A single-bit status
input pin (SREQ) can accessed using broadcast polling and
Broadcast Pulses embedded within each Interrogation are
also decoded.
5. MODE 7 (PROCEED)
If either the l-bus or the R-bus have been selected, the ESA
OBDH RBI-2 protocol mandates that a Mode 7 ‘Proceed’
instruction is given for every word transferred. The CTU can
transfer words in consecutive slots (fastest) or in ‘handshake’
mode for highest data integrity or in-between servicing other
OBDH users.
If the BT-bus has been selected, a Mode 7 ‘Proceed’
instruction starts the autonomous transfer of a block of data.
The RBl’s response to an ‘Input from l-bus’ Mode 7
‘Proceed’ instruction is the remaining DMA block length. When
the R-bus has been selected for a transfer, it carries the data
word in place of a response; consequently if ‘Input from R-bus’
is selected then no response is possible and if ‘Output to
R-bus’ is selected then the RBl’s response is the data word
requested from the CPU’s memory. If either ‘Input from BTbus’
or ‘Output to BT-bus’ is selected, the response associated the
‘Proceed’ instruction is the current RBI/user status (as for a
‘Read Status’ command).
RBI INSTRUCTION SET
The RBI only executes and responds to valid instructions
(tables 1, 2 and 3). Below is a description of the RBI instruction
modes (interrogation bits 12 to 14).
1. MODE O (READ STATUS)
Three Mode 0 commands (sent via the Interrogation bus)
can be used by the CTU to read the RBl’s DMA Address, block
Length or internal Status. The RBI responds (via the Response
bus) with the appropriate current setting obtained from the
RBl’s DMA controller and/or the user’s Service Request
(SREQ) and Bi-Level status (BIL(0:5)) input pins. The ‘Read
Status’ command also resets any DMA error reports.
Note: The data contained in any response is captured
shortly before the response is transmitted to ensure that it
contains current data and may be monitored at will during the
transfer process.
2. MODE 1 (INSTRUCT RBI/USER)
Mode 1 Interrogations sent by the CTU can be used to set
the RBI transfer bus selection, Programmed Address and/or
User Control Command (UCC(0:6)) output pins or to reset the
RBl’s DMA process. If this command is omitted, the next
transfer uses the last bus selection, etc. (see the flowchart,
Figure 9). Setting the Programmed Address to all-‘1’s causes it
to be disabled; specifying all-‘0’s causes no change to be
made. A UCC value of 127 will not be loaded; specifying this
value causes no change to be made.
For ‘Input from l-bus’ transfers, a continuous stream of
‘Address, Length, Proceed’ instructions may result (depending
on DMA access timing) in ‘Address, Length, Length’
responses which differ from those previously set up because
the first word transfer will commence in response to the
‘Proceed’ command. For output transfers, the address and
length responses will also be incremented and decremented
(respectively) by one word for R-bus transfers (two words for
BT-bus transfers) as the RBl’s DMA controller performs a
pre-fetch from the CPU’s memory in order to ensure that the
required data is available for transmission.
3. MODE 3 (LOAD START ADDRESS)
Mode 3 Interrogations load the RBl’s DMA Start Address
register. The associated response contains the RBl’s new
address provided that no data transfers have taken place
(using the ‘Proceed’ command) before it is transmitted. If this
instruction is omitted, the next transfer starts at the address
following the last address of the last transfer.
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