GP2021
include an allowance for this delay to reduce the iteration
time later.
Code DCO Programming
The following registers:
By using the data to time-tag theTIC, along with the values
of the Epoch counter, the Code generator phase, and the
Code clock phase it is possible to measure the time of the
SV signal in local apparent time. This gives the value of t1
needed for the pseudo-range measurement. The
pseudorange can now be computed as t12t2.
The CHx_CODE_DCO_INCR_HIGH
(or X_DCO_INCR_HIGH)
and CHx_CODE_DCO_INCR_LOW
are programmed in sequence with the relevant data
according to the estimated code frequency offset. It is
always necessary to write to both _HIGH and _LOW
registers. Code DCO programming will become effective
as soon as the channel is released (made active). If the
The error present in the time setting is the initial value of
the user clock bias, with an allowance for the various
counter phases. Once a Navigation Solution has been
found the clock error is precisely known and may be used
for future pseudorange calculations. Because the receiver
clock drifts with time, the clock bias changes with time and
must be tracked by the Navigation software.
channel
is
already
active,
writes
to
CHx_CODE_DCO_INCR_LOW are effective immediately.
(A short delay of up to 175ns will occur to allow
synchronisation of the processor write operation to the chip
operation).
CONTROLLING THE GP2021
Code Generator Programming
For each channel, the CHx_SATCNTL register is
programmed as follows:
The following section describes typical methods for
controlling the GP2021. These include signal acquisition
and tracking, carrier phase measurement and timemark
generation.
1. Set the SOURCESEL bit to select the input signal
source.
2. Set the TRACK_SEL bits to set the Tracking arm code
to either early or late (with respect to the Prompt arm).
3. Set the G2_LOAD bits to select the required PRN code.
4. Program the CHx_CODE_SLEW register with the
desired code phase offset. The slew operation will
become effective upon CHx_RSTB release. The first
DUMP will generate accumulated data for the channel
and set the associated CHx_NEW_ACCUM_DATA
status bit.
5. Release the relevant CHx_RSTB bits of the
RESET_CONTROL register to make the channel active.
When the code clock is inhibited (to slew the code
phase) the Integrate and Dump module is held reset. It
will start to accumulate correlation results only after the
slew operation is completed.
Search Operation
To perform signal acquistion, the carrier frequency and
code phase space needs to be searched until the signal is
detected. The maximum carrier frequency excursion from
its nominal value is defined by the maximum carrier Doppler
shift plus the maximum receiver clock error.The maximum
code phase is defined by the (fixed) code length. Typically,
all code phases will be searched at a given carrier
frequency before advancing to the next carrier frequency
bin and repeating the code phase search.
Carrier DCO Programming
The following registers:
CHx_CARRIER_DCO_INCR_HIGH
(or X_DCO _INCR_HIGH)
and CHx_CARRIER_DCO_INCR_LOW
A search for a satellite on more than one channel may be
performed using the MULTI channel addresses and
different code slew values as appropriate.
are programmed in sequence with the relevant data
according to the frequency bin being searched. It is always
necessary to write to both the _HIGH and _LOW registers.
Carrier DCO programming will become effective as soon
as the channel is released (made active).
Reading the Accumulated Data
At
each
DUMP
the
corresponding
CHx_NEW_ACCUM_DATA status bit is set in the
ACCUM_STATUS_A register.The status register, together
with all accumulation registers (CHx_l_TRACK,
CHx_Q_TRACK, CHx_l_PROMPT, CHx_Q_PROMPT)
are mapped into consecutive addresses. These can be
read as a consecutive block, if required, after every
ACCUM_INT interrupt. Alternatively, the Status Registers
may be polled. The Accumulation registers are not
If the channel is already active, writes to
CHx_CARRIER_DCO_INCR_LOW are effective
immediately. (A short delay of up to 175ns will occur, to
allow synchronisation of the processor write operation to
the chip operation.)
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