GP2021
DETAILED DESCRIPTION OF REGISTERS
GP2021 Register Map
The register map of the GP2021 is shown in Table 11. The
addresses are complete, and it should be noted that all the
register addresses are word-aligned, i.e. A0 and A1 are not
used. Adjacent register addresses thus increment by 4, in
ARM System Mode. However, in Standard Interface Mode,
the GP2021 address linesA<9:2> could be connected to the
processor address lines A<7:0>. Note that in this mode pins
A0 and A1 are allocated other functions.
Address (Hex)
Arm
Standard
interface
mode
Register
system
block
Registers
mode
A<22:20>
A<9:0>
A<9:2>
Correlator
CNTL
CNTL
CNTL
CNTL
CNTL
CNTL
CNTL
CNTL
CNTL
CNTL
CNTL
CNTL
CNTL
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
000 to 01C
020 to 03C
040 to 05C
060 to 07C
080 to 09C
0A0 to 0BC
0C0 to 0DC
0E0 to 0FC
100 to 11C
120 to 13C
140 to 15C
160 to 05C
180 to 19C
1A4
00 to 07
08 to oF
10 to 17
18 to 1F
20 to 27
28 to 2F
30 to 37
38 to 3F
40 to 47
48 to 4F
50 to 57
58 to 5F
60 to 67
69
CH0 Control
CH1 Control
CH2 Control
CH3 Control
CH4 Control
CH5 Control
CH6 Control
CH7 Control
CH8 Control
CH9 Control
CH10 Control
CH11 Control
MULTI Control
X_DCO_INCR_HIGH
PROG_ACCUM_INT
PROG_TIC_HIGH
PROG_TIC_LOW
ALL Control
TIMEMARK_CONTROL
TEST_CONTROL
MULTI_CHANNEL_SELECT
SYSTEM_SETUP
RESET_CONTROL
Status Registers
CH0 Accumulate
CH1 Accumulate
CH2 Accumulate
CH3 Accumulate
CH5 Accumulate
CH6 Accumulate
CH7 Accumulate
CH8 Accumulate
CH9 Accumulate
CH10 Accumulate
CH11 Accumulate
MULTI Accumulate
ALL Accumulate
1AC
1B4
1BC
6B
6D
6F
CNTL
1C0 to 1DC
1EC
70 to 77
7B
1F0
1F4
1F8
1FC
7C
7D
7E
7F
200 to 20C
210 to 21C
220 to 22C
230 to 23C
240 to 24C
260 to 26C
270 to 27C
280 to 28C
290 to 29C
2A0 to 2AC
2B0 to 2BC
2C0 to 2BC
2D0 to 2DC
2E0 to 2EC
80 to 83
84 to 87
88 to 8B
8C to 8F
90 to 93
98 to 9B
9C to 9F
A0 to A3
A4 to A7
A8 to AB
AC to AF
B0 to B3
B4 to B7
B8 to BB
ACCUM
ACCUM
ACCUM
ACCUM
ACCUM
ACCUM
ACCUM
ACCUM
ACCUM
ACCUM
ACCUM
ACCUM
ACCUM
Table 11 Register map
Cont…
28
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