GP2021
overwrite protected, therefore the system must respond
quickly when new data becomes available. Whether or
not it is necessary to process the accumulation at every
DUMP is dependent upon the application. The order of
reading them is optional, but ideally the CHx_Q_PROMPT
register should be read last, because this resets the
CHx_NEW_ACCUM_DATA bit.
to instigate this operation. The reading of measurement
data can be either interrupt driven or polled. For the interrupt
driven method the microprocessor reads the
ACCUM_STATUS_B or MEAS_STATUS_A register after
each MEAS_INT, and if the TIC bit is set, subsequently
reads the Measurement data. For the polled method the
ACCUM_STATUS_A register is always read following
every ACCUM_INT. In addition the ACCUM_STATUS_B
register is read on each ACCUM_INT to ensure no
Accumulated Data has been missed and to check the TIC
bit (along with several other status bits). The software tests
the TIC bit to determine if new Measurement Data is
available to be read.
The
CHx_MISSED_ACCUM
bits
in
the
ACCUM_STATUS_B register indicate that new
accumulated data has been missed. These can only be
cleared by a write to CHx_ACCUM_RESET or by
deactivating the channel.
Search on Other Code Phases
Preset Mode
When it is desired to correlate on the next code phase,
such as one whole chip later, the CODE_SLEW has to be
programmed with a value of 2 (the units are half code
chips). The slew will occur on the next DUMP. The effect
of CODE_SLEW is relative to the current code phase. To
repeat a CODE_SLEW, the register needs to be written to
again even if the same size slew is required.
Each channel can be programmed into PRESET mode
by writing a High into the PRESET/UPDATEB bit of the
CHx_SATCNTL register.
When a TIC occurs, the satellite code, epoch value and
slew numbers are loaded, and a new phase programmed
into the Code DCO regardless of its previous value. Prior
to the TIC the channel operates with its previous settings.
Preset Mode has no effect on the Carrier DCO and Carrier
Cycle Counter.
Once the signal has been detected (correlation threshold
exceeded), the code and carrier tracking loops can be
closed. The tracking loop parameters must be tailored in
the software to suit the application.
If Preset mode is initiated, it should be allowed to operate
to completion. The required sequence of operations is as
follows:
Data Bit Synchronisation
The data bit synchronisation algorithm should find the data
bit transition instant. The processor calculates the present
one millisecond epoch and programs this value into the
1MS_EPOCH counter. Ideally, epoch counter accesses
should occur following the reading of the accumulation
register at each DUMP.
1. Write into CHx_SATCNTLto select the PRESETmode,
together with the appropriate new settings.
2. Load the Code and Carrier DCO increment values.
Note: These will take effect immediately thereby
influencing the current measurements.
3. Load the following Registers:
Alternatively, the epoch counters can be left free-running
and the offset can be added by the software each time it
reads the epoch registers. Note that if the integration is
performed across bit boundaries, the integration result can
be very small.
CHx_CODE_DCO_PHASE, CHx_CODE_SLEW and
CHx_EPOCH_COUNT_LOAD. It is important that the
CHx_EPOCH_COUNT_LOAD occurs last, because it
enables the preset operation on the next TIC.
Interrupts
Reading the Measurement Data
There are 2 interrupt sources: ACCUM_INT and
MEAS_INT. Their sense is dependent upon the selected
microprocessor interface mode. The default ACCUM_INT
period is 505·.05µs. However, it can be reconfigured via
the PROG_ACCUM_INT register or by changing the
INTERRUPT_PERIOD or FRONT_END_MODE bits in the
SYSTEM_SETUP register.The default MEAS_INT period
is 50ms. However, this can be reconfigured via the
PROG_TIC_HIGH and PROG_TIC_LOW registers.
At each TIC, the measurement data is latched in the
Measurement Data registers:
CHx_EPOCH,
CHx_CODE_PHASE,
CHx_CARRIER_DCO_PHASE,
CHx_CARRIER_CYCLE_HIGH,
CHx_CARRIER_CYCLE_LOW,
CHx_CODE_DCO_PHASE.
Signal Path Delay Introduced by Hardware Signal
Processing
When it is desired to generate an accurate time reference
from GPS signals or to time-stamp position fixes the delays
in the receiver must be allowed for. The signal path delay
The ACCUM_STATUS_B or MEAS_STATUS_A register
must be polled at a rate greater than the TIC rate (to see if
a TIC has occurred), otherwise measurement data will be
lost. The ACCUM_INT or MEAS_INT events can be used
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