GP1020
SIGN &
2 MAG
MASTER CLK
SLAVE CLK
SAMP CLK
MASTER/SLAVE
CLOCK
GENERATOR
2
INPUT
SELECTOR
(DUAL
11 TO 7
MUX)
CLOCKS
TRACKING
MODULE
CHANNEL 1
TRACKING
MODULE
CHANNEL 2
TRACKING
MODULE
CHANNEL 3
TRACKING
MODULE
CHANNEL 4
TRACKING
MODULE
CHANNEL 5
TRACKING
MODULE
CHANNEL 6
TEST
SIGN &
MAG
8
7
8
7
BITE
INTERFACE
SELF TEST
GENERATOR
10 SETS OF
SIGN & MAG
INPUT
SIGNALS
7
STATUS
REGISTER
7
MICROPROCESSOR
BUS
7
STATISTICS
CHECK
TIC IN
INT IN
INT OUT
TIC OUT
TIMEMARK
TIMEBASE
GENERATOR
TIC
7
Fig. 10 Simplified overall block diagram
CH3, CH4, CH5 or CH6 inputs or registers. They have the
architecture shown in Fig. 11. The individual sub-blocks are as
follows:
CARRIER DCO
The Carrier DCO is an accumulator performing additions at a
constant rate and with a programmable increment value. It is
used to synthesise the digital local oscillator signal required to
bring the input signal to baseband in the mixer block, and must
be adjusted away from nominal to allow for Doppler shift and
crystal frequency error. The nominal frequency of the output is
1·405396825 MHz, set by loading the 26 bit CHx_CARR_INCR
register to 01F7B1B9
H
and is programmed with a resolution of
42·57475 milliHertz. The very fine resolution is needed to keep
the DCO in phase with the satellite signal.
CODE DCO
This block is a similar structure to the Carrier DCO block and
is used to synthesise the oscillator signal required to drive the
code generator at the proper chipping rate and phase. The
nominal frequency of the output is 2·046MHz, to give a chip rate
of 1·023MHz, and is set by loading the 25 bit CHx_CODE_INCR
register to 016EA4A8
H
and is programmed with a resolution of
85·14949 milliHertz. Again,the very fine resolution is needed to
keep the DCO in phase with the satellite signal.
CODE GENERATOR
This generates the processor-selected GPS Gold code (one
of PRN code numbers 1 to 32 for normal satellites or 33 to 37 for
ground based use) or the GLONASS code (fixed for all satellites)
or one of eight INMARSAT codes. Twin generators are used to
produce both a prompt (on-time) pattern and an early, late, or
early-minus-late version for tracking use. At the end of each code
sequence a signal DUMP is generated to latch the Accumulated
Data, separately for each channel.
MIXER AND CORRELATOR
The Mixer and Correlator first mixes the digitised input signal
with the Carrier DCO digital local oscillator to generate a signal
at baseband, and then uses the Code Generator outputs to
correlate the data stream. The block includes in-phase and
phase-quadrature channels, as well as prompt and dithered (or
early/late) correlator arms.
The term dither is used in the GP1020 to mean a code channel
in which the timing alternates one half-chip either before or after
the prompt channel, and not the now obsolete technique of Tau-
dither, in which the prompt arm timing is oscillated a little each
side of nominal to give tracking with only one arm.
QUADRUPLE INTEGRATE AND DUMP
The bit-by-bit results from the correlator are passed to the
Quadruple Integrate And Dump block, which integrates the
correlation result of individual code chips from all four correlators
(in-phase and phase-quadrature, prompt and dithered arms)
over a complete code period. Through the Accumulated Data
registers, the processor has access to each integration result.
NAVIGATION OR TIME REFERENCE RECEIVER
HARDWARE SYSTEM DESIGN
A receiver system can use one or more GP1020s. When only
one is used, that IC is operated in master mode, and when more
than one are used, one of them is designated as being the
master
and all of the others are operated as
slaves.
In all cases, the
master chip is the one which will receive the 40MHz MASTER
CLK from the GP1010 and generate, upon release of the
MASTERRESET signal, a gated 20MHz clock which drives all
slaves (if any) and allows a synchronised start-up. The master
device also generates the SAMP CLK signal which drives all of
the GP1010 front-ends.
The operating mode is programmed by tying the MASTER/
SLAVE pin to V
DD
for master or to V
SS
for slave operation. The
operating mode sets the functions of MASTER CLK, SLAVE
CLK and SAMP CLK pins.
The TIME MARK signal is generated by the master GP1020;
the slave TIME MARK generator, although not disabled, is not
synchronised with the master. The TIC signal is generated by the
master and routed to the slaves to ensure a common measure-
ment data sampling instant for all the tracking channels. The
slave TIC OUT signal is not disabled but is not used.
The master INT OUT drives the slaves’ INT IN pins to provide
latching of status bits at a common instant. Optionally, the slave
TIC OUT and INT OUT pins could be connected to the master
TIC IN and INT IN pins, respectively, for testing purposes.
When more than one GP1020 is used in the same system, the
devices must share a common TIC for sampling of measure-
ment data to enable the software to calculate clock bias in the
pseudoranges, and so find the correct ranges. Each GP1020
contains a state machine driven by 7 different clock phases,
so for two GP1020s to share a common TIC, the devices must
be synchronised. This is achieved by configuring the hard-
ware as follows:
•
•
All GP1020s share the same MASTERRESET signal.
One GP1020 is designated the master chip. It is
7
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
