GP1020
ELECTRICAL CHARACTERISTICS
These characteristics are guaranteed over the following conditions (unless otherwise stated):
Supply voltage, V
DD
= 5V
±10%;
Ambient Temperature, T
AMB
= 0°C to
170°C
(CG grade),240°C to
185°C
(IG grade).
DC CHARACTERISTICS
Characteristic
Min.
Supply current, I
DD
, chip fully active
CMOS inputs with pullup resistors to V
DD
: RTCINT,
MASTER/SLAVE, MARKFB (3:1), NANDA, NANDB,
WPROG, ALE
Input voltage high
Input voltage low
Pullup resistor
CMOS inputs with pulldown resistors to V
SS
: MOT/INTEL,
CLKSEL, INT IN, TIC IN
Input voltage high
Input voltage low
Pulldown resistor
CMOS inputs without either pullup or pulldown resistors:
MASTERRESET, CS, WEN, RW, MASTERCLK (note 1),
SLAVECLK, A (8:1), D (15:0), TCK, TDI, TMS, TRST
Input voltage high
Input voltage low
Input leakage current
TTL inputs with pullup resistors to V
DD
: SIGN (9:0),
MAG (9:0), PLLLOCKIN, GLONASSBIT
Input voltage high
Input voltage low
Pullup resistor
TTL inputs with pulldown resistors to V
SS
: TSCAN, TCKS,
TDI1, TMS1, TMS2
Input voltage high
Input voltage low
Pulldown resistor
Input for low level clocks: MASTERCLK (note 1)
Peak to peak sinewave
Power level 1 outputs: TMAG, TSIGN, TDO, TDO (7:1),
NANDOP
Output voltage high
Output voltage low
Power level 3 outputs: 100/219kHz, INT OUT, SAMPCLK,
TIC OUT, BITE CNTL, DISCOP, TIMEMARK
Output voltage high
Output voltage low
Power level 1 outputs with tri-state: MAG (9:2), SIGN (8:2),
TCK (7:1)
Output voltage high
Output voltage low
Output leakage current
Power level 3 output with tri-state: SLAVECLK
Output voltage high
Output voltage low
Output leakage current
Power level 6 output with tri-state: D (15:0)
Output voltage high
Output voltage low
Output leakage current
Bias output: BIAS
NOTE 1.
Value
Typ.
Max.
100
Units
mA
Conditions
0·8V
DD
20
75
0·2V
DD
250
V
V
kΩ
0·8V
DD
20
75
0·2V
DD
250
V
V
kΩ
0·8V
DD
1
0·2V
DD
10
V
V
µA
V
SS
<V
PIN
<V
DD
2·0
20
75
0·8
250
V
V
kΩ
2·0
20
600
V
DD
21
V
DD
20·5
0·2
75
0·8
250
V
V
kΩ
mV
V
V
AC coupled
I
OH
=
21·5mA
I
OL
= 1·5mA
I
OH
=
24·5mA
I
OL
= 4·5mA
0·4
V
DD
21
V
DD
20·5
0·2
0·4
V
V
V
DD
21
V
DD
20·5
0·2
V
DD
20·5
0·2
V
DD
20·5
0·2
0·4
10
0·4
10
0·4
10
V
V
µA
V
V
µA
V
V
µA
I
OH
=
21·5mA
I
OL
= 1·5mA
V
SS
<V
PIN
<V
DD
I
OH
=
24·5mA
I
OL
= 4·5mA
V
SS
<V
PIN
<V
DD
I
OH
=
29·0mA
I
OL
= 9·0mA
V
SS
<V
PIN
<V
DD
V
DD
21
V
DD
21
Special output to be used only as shown in Fig. 12 (page 8)
The input MASTERCLK may be driven by either CMOS logic levels or by a low amplitude sinewave if the BIAS pin is connected as shown
in Fig. 12.
4
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
