GP1020
Q_EOL
4
14-BIT ACCUMULATE
AND DUMP
Q_PROMPT
4
INPUT
SIGN & MAG
4·3MHz IF
SAMPLED
AT5·7MHz 2
TO GIVE
1·4MHz
INTO
GP1020
(VIA INPUT
SELECTOR)
QUADRATURE BASEBAND
Cos (vt)
1·4MHz
3
1
PROMPT C/A
EOL C/A
CODE
GENERATOR
CODE
DCO
EPOCH
COUNTERS
4
14-BIT ACCUMULATE
AND DUMP
MICROPROCESSOR BUS
CARRIER
DCO
Sin (vt)
1·4MHz
CARRIER CYCLE
COUNTER
CLOCK TIC
3
4
CLOCK TIC
I_PROMPT
4
CLOCK TIC
CLOCK TIC
IN-PHASE BASEBAND
14-BIT ACCUMULATE
AND DUMP
I_EOL
4
14-BIT ACCUMULATE
AND DUMP
Fig. 11 Tracking module simplified block diagram
programmed into this mode by tying the MASTER/SLAVE
pin to V
DD
(or by leaving it unconnected and relying on an
internal pull-up resistor.)
All other GP1020s are designated slaves and are
programmed into this mode by tying their MASTER/
SLAVE pin to V
SS
.
The master GP1020’s SAMP CLK output drives all
of the GP1010 front-ends. This ensures that in a multiple
GP1010 application, all of the signals are being sampled
at the same instant in all GP1010s. The slave GP1020s
have their SAMPLING CLK output left unconnected.
The SLAVE CLK output from the master drives the
SLAVE CLK inputs on all slaves.
•
•
•
GP1020
INTERNAL CIRCUIT
1-10n
MASTER CLK
600mV
FROM
GP1010
1k
5k
BIAS
10n
When the MASTERRESET is released, the clock generators
of all devices – master and slaves – are enabled. The SLAVE
CLK output of the master device will start to toggle only after the
master’s clock generator has reached a certain phase (200ns
after the MASTERRESET release). The clock generator of the
slave device gets reset into a state which corresponds to the next
phase and starts counting as soon as the SLAVE CLK signal
from the master reaches its SLAVE CLK input pin.
Fig. 12 Biasing circuit for master clock
SAMP CLK
40MHz47 = 5·7142857MHz output when the chip is in
master mode; nominal mark:space ratio is 1:1. This signal is held
low during an active MASTERRESET and when in slave mode.
TICOUT
Output signal from TIC generator, used to sample measure-
ment data and so initiate a navigation solution. TIC does not
drive the microprocessor directly but sets a flag in
MEAS_STATUS_A , which should be be examined by reading
the register periodically, such as at every INT OUT.
TIC OUT is active high; active time duration is either 4·54545ms
for a short TIC or 9·0909ms for a long TIC. The rising edge of TIC
OUT is in advance of the effective sampling instant inside the
device by 125ns. The TIC period is selectable via the TIC_PERIOD
bit of TIMER_CNTL register to either 100ms minus 100ns (=
99·9999ms) or to 9.0909 ms.
TIC IN
The TIC IN input of a GP1020 is normally provided by a
companion GP1020. Its use is controlled by the TIC_SOURCE
bit of the TIMER_CNTL register and is configured in most
applications so the master TIC OUT drives the slave TIC IN.
IMPORTANT TIMING SIGNALS IN A TYPICAL
HARDWARE DESIGN
MASTER CLK
The MASTER CLK is a 40MHz clock which sets the timing of
all functions in a GPS receiver using the GP1020. In a multiple
GP1020 system only the master is given this clock and this may
be connected in either of two ways, depending on the signal
level. If the clock is a TTL signal it is directly connected to the
MASTER CLK input and the BIAS output pin is left unconnected.
The other option is an AC-coupled 600 mV peak-to-peak signal,
when the BIAS output is used to set the DC voltage of the
MASTER CLK pin as shown in Fig. 12. The MASTER CLK pin on
each slave GP1020 is not used and should be tied to V
DD
or V
SS
.
SLAVE CLK
20MHz with 1:1 nominal mark:space ratio. Output from
master GP1020, input to slave, using a bidirectional buffer
controlled by MASTER/SLAVE. This signal is held low when the
master chip is reset and starts to toggle within 200ns after
MASTERRESET is released.
8
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
