GP1020
INT OUT
This output signal is a free running interrupt timebase which
may be used to interrupt the microprocessor to initiate data
transfer sufficiently often that no correlation results will be
missed. The tracking loops rely on the microprocessor to adjust
the DCO registers in response to signal changes so the rate of
interaction must be sufficiently high. If the frequency of INT
OUTis too high for the software to process then a polling scheme
may be used, by inhibiting the interrupts (INT_MASK bit in
TIMER_CNTL set low) and then periodically writing to
STATUS_LATCH and reading the status registers to check if
new data is available.
The period of INT OUT is programmable; a typical value is
505·05µs. During MASTERRESET the interrupt output is stopped
and the pin is held LOW if in Intel mode, or HIGH if in Motorola
mode. The active duration of INT OUT (HIGH for Intel, LOW for
Motorola) is 252·525µs, which should be more than adequate to
ensure that the interrupt controller in the processor will have time
to respond.
INT IN
This input signal is normally provided by the INT OUT output
of a companion GP1020; in general the master drives the slave.
It is used, when selected via the INT_SOURCE bit of the
TIMER_CNTL register, to latch the state of the status bits.
100kHz/219kHz
A clock output at either 100kHz or 219kHz which may be used
to drive the microprocessor interrupt timer. The frequency is set
by the level on CLKSEL (HIGH for 100kHz and LOW for 219kHz).
MASTERRESET
When MASTERRESET is set LOW , all the registers, accu-
mulators and counters are cleared, except CHX_CNTL, which IS
initialised to specific values (refer to detailed description of the
registers for these values). When the device is held reset, by
MASTERRESET set low, the following pins are driven as listed:
MASTER CLK:
This input may or may not be being exter-
nally driven during the reset.
MASTERRESET internally gates MASTER
CLK to ensure a well defined level on all
clock lines until the release of
MASTERRESET; the release of
MASTERRESET must occur only when the
input buffer is properly biased and the input
signal is stable.
SLAVE CLK:
Configured as an input on slave devices and
held LOW on master device.
SAMP CLK:
Held LOW.
100/219kHz:
This output is held LOW when MASTER
RESET is active (also LOW) and toggles to
HIGH shortly after MASTERRESET is
released, and then runs normally.
D0-D15:
High impedance.
BITE CNTL:
DISC OP:
TIC OUT:
INT OUT:
LOW.
LOW.
LOW.
This output is held LOW until interrupt inhibit
is removed, when in Intel bus type mode, or
is held HIGH until the inhibit is re-
moved, when in Motorola bus type mode.
(e.g. ARINC 743 may be wanted) or a simple reference time
clock may be built.
To synchronise TIME MARK to GPS time the first stage is to
acquire the measurement data at any arbitrary TIC and then
calculate the full navigation solution to give the time at that TIC.
From this determine a later TIC at which to acquire data again
such that after the navigation solution computation delay (typi-
cally a few TIC periods long) a further delay may be programmed
into DOWN_COUNT_HI and _LO registers to start on the next
TIC, to give TIME MARK at the required GPS whole second. This
is rather a long process to get started, but once the first correct
TIC choice and down counter delay are known the process can
roll on with each TIC and delay calculation coming from the
previous navigation solution.
To get UTC instead of GPS time it is only neccessary to read
the navigation message to get the number of whole seconds
difference and add this to the calculated GPS time. A possible
refinement is to calculate the oscillator drift over several meas-
urements and use this to extrapolate a better value for the delay
counter. The ultimate accuracy that can be achieved is very
good, but to get this the crystal must both have high stability and
be drift compensated in the software; in addition, the receiver
front-end delay must be known and allowed for, and the delay
through the output drivers and cables must be allowed for by
using the MARKFBx pins.
If, as is likely, Selective Availability is on it will be the main
source of error in a well designed TIME MARK system, but better
than one microsecond absolute accuracy is still possible. To
reduce the effects of SA it is possible to use a stable rubidium
reference oscillator and average the induced offsets over a long
time to give very good peak errors of a few tens of nanoseconds.
As the main purpose of the TIME MARK output is a timing
reference signal at one pulse per second for the electronic
systems in an airliner, it must be both accurate and known to be
accurate.
The accuracy is achieved by loading DOWN_COUNT_HI
and _LO with the correct offset in 50ns units from the GPS
measuring TIC. As the TIC rate is nominally 1ppm less than
10Hz, the DOWN_COUNT value should be expected to in-
crease at around 1µs per one second TIME MARK, a number
change of
120
each pulse. This value will need continuous fine
tuning to allow for the stable and variable crystal errors.
Integrity is ensured in two ways; first, by using PROP_DELAY
to check the delay through line drivers and to verify that a TIME
MARK really did occur and, secondly, by having a complex
handshake sequence so that any failure in the hardware will be
detected by the microprocessor. The handshake sequence is:
1.
Write to DOWN_COUNT_LO to arm the TIME MARK gen-
erator (this requires that DOWN_COUNT_HI is already
written; as it rarely changes,this is often automatically true).
2.
At next TIC the GP1020 will start DOWN_COUNT.
3.
The GP1020 will give a TIME MARK pulse output and start
the PROP_DELAY counter.
4.
Feed TIME MARK back through MARK_FBx input to stop
PROP_DELAY and to set MARK_FB_ACK in
MEAS_STATUS_A
5.
Read MEAS_STATUS_A, normally as part of the Measure-
ment Data transfer protocol but, on this occasion, to also
clear the overwrite protection on PROP_DELAY and to clear
the MARK_FB_ACK bit.
6.
Read PROP_DELAY, once MARK_FB_ACK has been set
(and cleared) to give a stable value for the last delay. This
also re-enables the TIME MARK generator ready for a repeat
of step (1) to take effect.
This may seem rather complicated, but is only needed once
per second and so is little overhead if a simple system is all
that is required. For a full accuracy system, the various
register operations fit in with the computations needed to
achieve full ARINC 743 specification.
TIME MARK
The primary purpose of the TIME MARK output is to give a
one pulse per second signal locked to UTC or GPS time. This
may be followed by the correct time from the microprocessor and
could be used as a reference by other navigation instruments
9
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