GP1020
GP1020 BUS TIMING DIAGRAMS (continued)
WEN
t
CVWRV
CS
t
ALVWRV
ALE
t
AVWRV
A (8:1)
t
AHOLD
ADDRESS VALID
WEN
t
WRHCH
t
WLWH
t
CVWRV
CS
t
WRHCH
t
CHALV
NEXT
R/W
t
ALVWRV
ALE
t
AVWRV
A (8:1)
t
AHOLD
ADDRESS VALID
t
CHALV
NEXT
R/W
t
DSETUP
D (15:0)
t
RWVWENH
RW
t
DHOLD
t
RVDV
D (15:0)
t
RWVWENH
RW
DATA VALID
t
RHDZ
DATA VALID
t
WENLRWNV
t
WENLRWNV
Fig. 8 Motorola 68xxx mode WRITE. MOT/INTEL = 1,
WPROG = 0
Fig. 9 Motorola 68xxx mode READ. MOT/INTEL = 1,
WPROG = 0
SIGNAL PROCESSING OVERVIEW
Each channel of the GP1020 is fed with a 2-bit (or optionally
with a 1-bit) GPS digital IF at around 1·4MHz, from the input
multiplexer that connects one of ten signal sources to the
channel input. This signal is first brought to baseband using an
on-chip digital mixer driven by a programmable digital local
oscillator. It is then correlated with a C/A code internally gener-
ated by a programmable Gold code generator; the correlation
result is the sum of the comparisons of individual code chips over
a complete code period (an ‘epoch’ in GPS terminology). A large
positive or a large negative sum indicate good correlation but
with opposite modulation, where the size of ‘large’ will depend on
the current signal to noise ratio, while a small sum indicates poor
correlation and the need to adjust the loops or choose another
satellite.
These results form the ‘Accumulated Data’ and are made
available to the microprocessor to both control the tracking loops
and to give the broadcast satellite data, the ‘Navigation Mes-
sage’ when demodulated. Periodically, the code epoch count,
the code phase, and the carrier phase of all channels, are
sampled at the same instant to form the ‘Measurement Data’ and
are also made available to the processor.
TIMEBASE GENERATOR
The Time Base Generator produces, among other signals: a
505·05
µs
free-running interrupt timebase INT OUT, a free-
running TIC OUT signal with a period which may be selected to
be either 100ms or 9·09ms (approximately), and a TIME MARK
signal with a 1 second period as an output which may be locked
to GPS time, UTC, or the receiver timebase by programming its
delay relative to the TIC, based on recent navigation solutions.
The TIC is mainly used to latch measurement data (epoch count,
code phase, code DCO phase and integrated carrier phase
( = DCO phase and cycle count)) of all six channels at the same
instant.
BITE INTERFACE
The Bite Interface block contains a register which allows
control over the built-in-test functions of the chip. In addition, this
register allows the processor to read the state of discrete input
pins, such as PLLLOCKIN connected to the status output of the
GP1010, and also to set the state of the BITE CNTL and the
DISCOP output pins. These can in turn, for example, be used to
drive the GP1010 BITE input pin and the LNA power on/off
select, respectively.
STATUS REGISTERS
The Status Registers block contains registers describing the
status of accumulated and measurement data provided by each
channel.
SIGNAL SELECTION BLOCK
The Signal Selection block contains a multiplexer which can
be programmed to direct any of the ten input sources to any of
the six tracking channels. This is needed in GLONASS where
frequency division multiplexing is used and separate local oscil-
lators are needed to receive each satellite, leading to separate
IF filter channels. An input selector may be desirable in GPS,
which uses code division multiplexing, to allow the use of multiple
antennae to overcome problems of incomplete sky visibility.
For SIGN inputs, LOW =
2,
HIGH =
1;
for MAG inputs,
LOW = 1, HIGH = 3.
DESCRIPTION OF BLOCKS (see Fig. 10)
CLOCK GENERATOR
The Clock Generator block generates the various clocks
required in the GP1020, which can be operated either as a
master or as a slave device. When it is operated as a master, the
Clock Generator block is driven by a 40MHz clock provided by
the accompanying front-end chip, the GP1010, and to drive the
slaves a 20MHz output SLAVE CLK is provided. When the
GP1020 is operated as a slave, it is driven only by this 20MHz
SLAVE CLK from the master device. In the master the
40MHz is divided in a counter to form seven clock phases to
control the data flow, but to get the same timing in the slaves twin
20MHz dividers use both high and low phases separately to give
the effect of 40MHz clocking.
When in master mode these seven phases are also used to
generate a sampling clock (SAMP CLK) output at 40MHz47 =
5·71MHz, which drives the data sampling clock input of the
GP1010. A 100/219kHz output is provided for use as a micro-
processor Programmable Interrupt Clock.
TRACKING MODULE BLOCKS
The six Tracking Module blocks are all identical so that the
term CHx is used in the description to mean any of CH1, CH2,
6
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