GP1020
PIN DESCRIPTIONS (See Application Notes, p. 41)
All V
SS
and all V
DD
pins must be used in order to ensure
reliable operation. Several pins, such as Satellite Inputs 2 to
9 Sign and Magnitudes are also used for device testing, but
only as a secondary function.
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
Pin
No.
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Signal
name
TICIN
TICOUT
D0
D1
V
SS
V
DD
D2
D3
TIME MARK
RTCINT
MARKFB1
MARKFB2
D4
D5
V
DD
V
SS
D6
D7
WPROG
NANDA
NANDB
TDO
TCK
TRST
NANDOP
TMS
TDI
MARKFB3
TDO7
DISCOP
TDO6
TDO5
D8
D9
V
SS
V
DD
D10
D11
TDO4
TDO3
TDO2
TDO1
D12
D13
V
DD
V
SS
D14
D15
ALE
A1
A2
A3
A4
A5
A6
Type
I
O
I/O
I/O
2
1
I/O
I/O
O
I
I
I
I/O
I/O
1
2
I/O
I/O
I
I
I
O
I
I
O
I
I
I
O
O
O
O
I/O
I/O
2
1
I/O
I/O
O
O
O
O
I/O
I/O
1
2
I/O
I/O
I
I
I
I
I
I
I
Description
TIC input to slave
TIC output from Master
Data Bus, bit 0
Data Bus, bit 1
Ground
Positive supply
Data Bus, bit 2
Data Bus, bit 3
One pulse per second output
Real time clock interrupt input
Timemark line driver feedback
Timemark line driver feedback
Data Bus, bit 4
Data Bus, bit 5
Positive supply
Ground
Data Bus, bit 6
Data Bus, bit 7
Bus timing mode - see note 2
Test Structure - see note 3
Test Structure - see note 3
Boundary Scan output
Boundary Scan clock
Boundary Scan reset
Test Structure - see note 3
Boundary Scan control
Boundary Scan input
Timemark line driver feedback
Serial Test Data Output 7
On/Off control for LNA by GP1010
Serial Test Data Output 6
Serial Test Data Output 5
Data Bus, bit 8
Data Bus, bit 9
Ground
Positive supply
Data Bus, bit 10
Data Bus, bit 11
Serial Test Data Output 4
Serial Test Data Output 3
Serial Test Data Output 2
Serial Test Data Output 1
Data Bus, bit 12
Data Bus, bit 13
Positive supply
Ground
Data Bus, bit 14
Data Bus, bit 15
Address Latch Enable,
bus control
Register Address, bit 1 (LSB)
Register Address, bit 2
Register Address, bit 3
Register Address, bit 4
Register Address, bit 5
Register Address, bit 6
Signal
name
A7
A8
MASTER/
SLAVE
TSCAN
TCKS
TDI1
MASTER
RESET
MOT/INTEL
CS
V
SS
V
DD
WEN
RW
TMS2
TMS1
TMAG
TSIGN
MAG2
100/219kHz
V
DD
V
SS
INTOUT
SIGN2
MAG3
SIGN3
MAG4
SIGN4
MAG5
SIGN5
MAG6
SIGN6
MAG7
SIGN7
MAG8
SIGN8
MAG9
SIGN9
MAG1
SIGN1
V
SS
V
DD
MAG0
SIGN0
SAMPCLK
V
DD
MASTERCLK
V
SS
Bias
V
SS
V
DD
V
SS
CLKSEL
PLLLOCKIN
BITECNTL
GLONASSBIT
SLAVECLK
INTIN
TCK1
TCK2
TCK3
TCK4
TCK5
TCK6
TCK7
TCK8
Type
I
I
I
I
I
I
I
I
I
2
1
I
I
I
I
O
O
I/O
O
1
2
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
1
I
I
O
1
I
2
O
2
1
2
I
I
O
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Description
Register Address, bit 7
Register Address, bit 8
Master or slave mode select
Scan Test mode select
Test Clock select
Serial Test Data Input
Master Reset (active low)
Motorola (hi) or Intel (lo) bus select
Chip Select (active low) for bus
Ground
Positive supply
Bus control - see note 1
Bus control - see note 1
Test Mode Select 2
Test Mode Select 1
Test PRN Pattern Magnitude o/p
Test PRN Pattern Sign output
Satellite Input 2, Magnitude
Programmable Interrupt Timer clock
Positive supply
Ground
Interrupt out to microprocessor
Satellite Input 2, Sign
Satellite Input 3, Magnitude
Satellite Input 3, Sign
Satellite Input 4, Magnitude
Satellite Input 4, Sign
Satellite Input 5, Magnitude
Satellite Input 5, Sign
Satellite Input 6, Magnitude
Satellite Input 6, Sign
Satellite Input 7, Magnitude
Satellite Input 7, Sign
Satellite Input 8, Magnitude
Satellite Input 8, Sign
Satellite Input 9, Magnitude
Satellite Input 9, Sign
Satellite Input 1, Magnitude
Satellite Input 1, Sign
Ground
Positive supply
Satellite Input 0, Magnitude
Satellite Input 0, Sign
Sampling clock to down-converter
Positive supply
40MHz Master Clock
Ground
Bias for MASTERCLK in 600mV
AC-coupled mode
Ground
Positive supply
Ground
Sets 100/219kHz to 100or 219kHz
PLL lock status from down-converter
BITE control to down-converter
I/P to monitor GLONASS front-end
20MHz clock from Master to slave
Interrupt to slave to sync to Master
Test Clock 1
Test Clock 2
Test Clock 3
Test Clock 4
Test Clock 5
Test Clock 6
Test Clock 7
Test Clock 8
NOTE 1.
The functions of RW and WEN pins depend on whether the
GP1020 is in Motorola™ (MOT/INTEL = ‘1’) or Intel™ mode (MOT/INTEL
= ‘0’). In Motorola mode, WEN is an enable (active high) and RW is Read/
Write select (‘1’ = Read). In Intel mode RW is Read, active low, and WEN
is Write, also active low.
MOT/INTEL
1
1
0
0
Mode
Motorola
Motorola
Intel
Intel
WEN
1
1
1
0
RW
0
1
0
1
Function
Write
Read
Read
Write
NOTE 2.
WPROG is used to modify the timing of bus operations; when it
is held HIGH the internal write signal is ORed with ALE to allow time for the
internal address lines to stabilise; when it is held LOW there is no delay
added to write.
NOTE 3.
NANDOP (pin 90) is the output of a spare gate with
inputs on NANDA (pin 85) and NANDB (pin 86).
3
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
