R
XCR3064A: 64 Macrocell CPLD With Enhanced Clocking
AC Electrical Characteristics1 For Commercial Grade Devices
Commercial: 0°C ≤ T
≤ +70°C; 3.0V ≤ V ≤ 3.6V
AMB
CC
7
10
Symbol
Parameter
Unit
Min. Max. Min. Max.
t
t
Propagation delay time, input (or feedback node) to output through PAL
2
3
7.5
9
2
3
10
ns
ns
PD_PAL
PD_PLA
Propagation delay time, input (or feedback node) to output through
PAL + PLA
11.5
t
t
t
t
t
t
t
t
f
f
f
t
t
Clock to out (global synchronous clock from pin)
2
3.5
5
5.5
2
5
7
0
ns
ns
CO
Setup time (from input or feedback node) through PAL
Setup time (from input or feedback node) through PAL + PLA
SU_PAL
SU_PLA
H
6.5
ns
2
Hold time
0
ns
2
Clock High time
2
2
2.5
2.5
ns
CH
2
Clock Low time
ns
CL
2
Input Rise time
100
100
100
100
ns
R
2
Input Fall time
ns
F
2
Maximum FF toggle rate (1/t + t
)
250
143
111
200
105
83
MHz
MHz
MHz
ns
MAX1
MAX2
MAX3
BUF
PDF_PAL
CH
CL
2
Maximum internal frequency (1/t
+ t
)
SUPAL
CF
2
Maximum external frequency (1/t
+ t
)
SUPAL
CO
2
Output buffer delay time
2
2
8
Input (or feedback node) to internal feedback node delay time through
5.5
ns
2
PAL
t
Input (or feedback node) to internal feedback node delay time through
PDF_PLA
7
9.5
ns
2
PAL+PLA
2
t
t
Clock to internal feedback node delay time
CF
3.5
20
4.5
20
ns
µs
ns
ns
ns
ns
2
Delay from valid V to valid reset
INIT
CC
2, 3
t
t
t
t
Input to output disable
ER
EA
RP
RR
8
8
9
9
9.5
9.5
9.5
9.5
2
Input to output valid
2
Input to register preset
2
Input to register reset
Notes:
1. Specifications measured with one output switching. See Figure 6 and Table 6 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5 pF.
11
www.xilinx.com
DS037 (v1.1) February 10, 2000
1-800-255-7778
XILINX [ XILINX, INC ]
