R
XCR3064A: 64 Macrocell CPLD With Enhanced Clocking
AC Electrical Characteristics
1
For Industrial Grade Devices
Industrial: -40
°
C
≤
T
AMB
≤
+85
°
C; 2.7V
≤
V
CC
≤
3.6V
Symbol
t
PD_PAL
t
PD_PLA
t
CO
t
SU_PAL
t
SU_PLA
t
H
t
CH
t
CL
t
R
t
F
f
MAX1
f
MAX2
f
MAX3
t
BUF
t
PDF_PAL
t
PDF_PLA
t
CF
t
INIT
t
ER
t
EA
t
RP
t
RR
Notes:
1. Specifications measured with one output switching. See
Figure 6
and
Table 6
for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output C
L
= 5 pF.
Min.
Propagation delay time, input (or feedback node) to output through PAL
2
Propagation delay time, input (or feedback node) to output through
3
PAL + PLA
Clock to out (global synchronous clock from pin)
2
Setup time (from input or feedback node) through PAL
5
Setup time (from input or feedback node) through PAL + PLA
6.5
2
Hold time
Clock High time
3
Clock Low time
3
Input Rise time
Input Fall time
Maximum FF toggle rate
2
(1/t
CH
+ t
CL
)
166
2
Maximum internal frequency (1/t
SUPAL
+ t
CF
)
111
2
Maximum external frequency (1/t
SUPAL
+ t
CO
)
90
2
Output buffer delay time
Input (or feedback node) to internal feedback node delay time through
PAL
2
Input (or feedback node) to internal feedback node delay time through
PAL+PLA
2
Clock to internal feedback node delay time
2
Delay from valid V
CC
to valid reset
2
Input to output disable
2, 3
Input to output valid
2
Input to register preset
2
Input to register reset
2
Parameter
10
Max.
10
11.5
7
Min.
2
3
2
6
7.5
3.5
3.5
100
100
143
95
77
2
8
9.5
5
20
10
10
10
10
12
Max.
12
13.5
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
µ
s
ns
ns
ns
ns
0
0
100
100
2
9
10.5
5.5
20
12
12
12
12
13
www.xilinx.com
1-800-255-7778
DS037 (v1.1) February 10, 2000
XILINX [ XILINX, INC ]
