R
Platform Flash In-System Programmable Configuration PROMS
input, then the pin should be tied High.
PROM asserts its CEO output Low and drives its outputs to
a high-impedance state. The second PROM recognizes the
Low level on its CE input and immediately enables its out-
(1)
FPGA SelectMAP (Parallel) Device Chaining
puts.
Multiple Virtex-II FPGAs can be configured using the
SelectMAP mode, and be made to start up simultaneously.
To configure multiple devices in this way, wire the individual
CCLK, DONE, INIT, Data ([D0..D7]), Write (WRITE or
RDWR_B), and BUSY pins of all the devices in parallel. If all
devices are to be configured with the same bitstream, read-
back is not being used, and the CCLK frequency selected
does not require the use of the BUSY signal, the CS_B pins
can be connected to a common line so all of the devices are
configured simultaneously (Figure 13).
After configuration is complete, address counters of all cas-
caded PROMs are reset if the PROM OE/RESET pin goes
Low or CE goes High.
When utilizing the advanced features for the XCFxxP Plat-
form Flash PROM, including the clock output (CLKOUT)
option, decompression option, or design revisioning, pro-
gramming files which span cascaded PROM devices can
only be created for cascaded chains containing only
XCFxxP PROMs. If the advanced features are not used,
then cascaded PROM chains can contain both XCFxxP and
XCFxxS PROMs.
With additional control logic, the individual devices can be
loaded separately by asserting the CS_B pin of each device
in turn and then enabling the appropriate configuration data.
The PROM can also store the individual bitstreams for each
FPGA for SelectMAP configuration in separate design revi-
sions. When design revisioning is utilized, additional control
logic can be used to select the appropriate bitstream by
asserting the EN_EXT_SEL pin, and using the
REV_SEL[1:0] pins to select the required bitstream, while
asserting the CS_B pin for the FPGA the bitstream is target-
ing (Figure 14).
Initiating FPGA Configuration
The options for initiating FPGA configuration via the Plat-
form Flash PROM include:
1. Automatic configuration on power up
2. Applying an external PROG_B (or PROGRAM) pulse
3. Applying the JTAG CONFIG instruction
Following the FPGA’s power-on sequence or the assertion
of the PROG_B (or PROGRAM) pin the FPGA’s configura-
tion memory is cleared, the configuration mode is selected,
and the FPGA is ready to accept a new configuration bit-
stream. The FPGA’s PROG_B pin can be controlled by an
external source, or alternatively, the Platform Flash PROMs
incorporate a CF pin that can be tied to the FPGA’s
PROG_B pin. Executing the CONFIG instruction through
JTAG pulses the CF output Low once for 300-500 ns, reset-
ting the FPGA and initiating configuration. The iMPACT soft-
ware can issue the JTAG CONFIG command to initiate
FPGA configuration by setting the "Load FPGA" option.
For clocking the parallel configuration chain, either the first
FPGA in the chain can be set to Master SelectMAP, gener-
ating the CCLK, with the remaining devices set to Slave
SelectMAP, or all the FPGA devices can be set to Slave
SelectMAP and an externally generated clock can be used
to drive the configuration interface. Again, the respective
device data sheets should be consulted for detailed infor-
mation on a particular FPGA device, including which config-
uration modes are supported by the targeted FPGA device.
Cascading Configuration PROMs
When configuring multiple FPGAs in a serial daisy chain,
configuring multiple FPGAs in a SelectMAP parallel chain,
or configuring a single FPGA requiring a larger configura-
tion bitstream, cascaded PROMs provide additional mem-
ory (Figure 10, Figure 13, Figure 14, and Figure 15).
Multiple Platform Flash PROMs can be concatenated by
using the CEO output to drive the CE input of the down-
stream device. The clock signal and the data outputs of all
Platform Flash PROMs in the chain are interconnected.
After the last data from the first PROM is read, the first
When using the XCFxxP Platform Flash PROM with design
revisioning enabled, the CF pin should always be connected
to the PROG_B (or PROGRAM) pin on the FPGA to ensure
that the current design revision selection is sampled when
the FPGA is reset. The XCFxxP PROM samples the current
design revision selection from the external REV_SEL pins
or the internal programmable Revision Select bits on the ris-
ing edge of CF. When the JTAG CONFIG command is exe-
cuted, the XCFxxP will sample the new design revision
before initiating the FPGA configuration sequence. When
using the XCFxxP Platform Flash PROM without design
revisioning, if the CF pin is not connected to the FPGA
PROG_B (or PROGRAM) pin, then the XCFxxP CF pin
should be tied High.
1. The SelectMAP (Parallel) FPGA configuration modes are sup-
ported only by the XCFxxP Platform Flash PROM.These modes
are not supported by the XCFxxS Platform Flash PROM.
DS123 (v2.4) July 20, 2004
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
13
XILINX [ XILINX, INC ]
