R
Platform Flash In-System Programmable Configuration PROMS
Typically, a wide range of frequencies can be selected for
the FPGA’s internally generated CCLK which always starts
at a slow default frequency. The FPGA’s bitstream contains
configuration bits which can switch CCLK to a higher fre-
quency for the remainder of the Master Serial configuration
sequence. The desired CCLK frequency is selected during
bitstream generation.
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The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
The OE/RESET pins of all PROMs are connected to
the INIT_B (or INIT) pins of all FPGA devices. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration.
The PROM CE input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
•
Connecting the FPGA device to the configuration PROM for
Master Serial Configuration Mode (Figure 8):
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
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•
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The DATA output of the PROM(s) drive the DIN input of
the lead FPGA device.
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s)
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
DATA output active and causes an unnecessary I
CC
active supply current (DC Characteristics Over
Operating Conditions).
The PROM CF pin is typically connected to the FPGA's
PROG_B (or PROGRAM) input. For the XCFxxP only,
the CF pin is a bidirectional pin. If the XCFxxP CF pin is
not connected to the FPGA's PROG_B (or PROGRAM)
input, then the pin should be tied High.
•
The OE/RESET pins of all PROMs are connected to
the INIT_B pins of all FPGA devices. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration.
•
The PROM CE input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
Serial Daisy Chain
Multiple FPGAs can be daisy-chained for serial configura-
tion from a single source. After a particular FPGA has been
configured, the data for the next device is routed internally
to the FPGA’s DOUT pin. Typically the data on the DOUT
pin changes on the falling edge of CCLK, although for some
devices the DOUT pin changes on the rising edge of CCLK.
Consult the respective device data sheets for detailed infor-
mation on a particular FPGA device. For clocking the
daisy-chained configuration, either the first FPGA in the
chain can be set to Master Serial, generating the CCLK,
with the remaining devices set to Slave Serial (Figure 10),
or all the FPGA devices can be set to Slave Serial and an
externally generated clock can be used to drive the FPGA's
configuration interface.
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
DATA output active and causes an unnecessary I
CC
active supply current (DC Characteristics Over
Operating Conditions).
The PROM CF pin is typically connected to the FPGA's
PROG_B (or PROGRAM) input. For the XCFxxP only,
the CF pin is a bidirectional pin. If the XCFxxP CF pin is
not connected to the FPGA's PROG_B (or PROGRAM)
input, then the pin should be tied High.
•
FPGA Slave Serial Mode
In Slave Serial mode, the FPGA loads the configuration bit-
stream in bit-serial form from external memory synchro-
nized by an externally supplied clock. Upon power-up or
reconfiguration, the FPGA's mode select pins are used to
select the Slave Serial configuration mode. Slave Serial
Mode provides a simple configuration interface. Only a
serial data line, a clock line, and two control lines (INIT and
DONE) are required to configure an FPGA. Data from the
PROM is read out sequentially on a single data line (DIN),
accessed via the PROM's internal address counter which is
incremented on every valid rising edge of CCLK. The serial
bitstream data must be set up at the FPGA’s DIN input pin a
short time before each rising edge of the externally provided
CCLK.
(1)
FPGA Master SelectMAP (Parallel) Mode
In Master SelectMAP mode, byte-wide data is written into
the FPGA, typically with a BUSY flag controlling the flow of
data, synchronized by the configuration clock (CCLK) gen-
erated by the FPGA. Upon power-up or reconfiguration, the
FPGA's mode select pins are used to select the Master
SelectMAP configuration mode. The configuration interface
typically requires a parallel data bus, a clock line, and two
control lines (INIT and DONE). In addition, the FPGA’s Chip
Select, Write, and BUSY pins must be correctly controlled to
enable SelectMAP configuration. The configuration data is
read from the PROM byte by byte on pins [D0..D7],
accessed via the PROM's internal address counter which is
incremented on every valid rising edge of CCLK. The bit-
Connecting the FPGA device to the configuration PROM for
Slave Serial Configuration Mode (Figure 9):
•
The DATA output of the PROM(s) drive the DIN input of
the lead FPGA device.
1. The Master SelectMAP (Parallel) FPGA configuration mode is sup-
ported only by the XCFxxP Platform Flash PROM. This mode is not
supported by the XCFxxS Platform Flash PROM.
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The PROM CLKOUT (for XCFxxP only) or an external
clock source drives the FPGA's CCLK input.
DS123 (v2.4) July 20, 2004
Preliminary Product Specification
www.xilinx.com
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11
XILINX [ XILINX, INC ]
