Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Description
Date
Version
06/01/2012
1.3
Reorganized entire data sheet including adding Table 43 and Table 47.
UpdatedTSOLin Table 1. UpdatedIBATT andaddedRIN_TERM to Table 3. UpdatedPower-On/OffPower
Supply Sequencing section with regards to GTP transceivers. In Table 8, updated many parameters
including SSTL135 and SSTL135_R. Removed VOX column and added DIFF_HSUL_12 to Table 10.
Updated VOL in Table 11. Updated Table 15 and removed notes 2 and 3. Updated Table 16.
Updated the AC Switching Characteristics based upon the ISE 14.1 software v1.03 for the -3, -2, -2L
(1.0V), -1, and v1.01 for the -2L (0.9V) speed specifications throughout the document.
In Table 30, updated Reset Delays section including Note 10 and Note 11. In Table 56, replaced
F
TXOUT with FGLK. Updated many of the XADC specifications in Table 65 and added Note 2. Updated
and moved Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK section from
Table 66 to Table 37 and Table 38.
09/20/2012
1.4
In Table 1, updated the descriptions, changed VIN and Note 2, and added Note 4. In Table 2, changed
descriptions and notes. Updated parameters in Table 3. Added Table 4. Revised the Power-On/Off
Power Supply Sequencing section. Updated standards and specifications in Table 8, Table 9, and
Table 10. Removed the XC7A350T device from data sheet.
Updated the AC Switching Characteristics section to the ISE 14.2 speed specifications throughout the
document. Updated the IOB Pad Input/Output/3-State discussion and changed Table 18 by adding
T
IOIBUFDISABLE. Removed many of the combinatorial delay specifications and TCINCK/TCKCIN from
Table 27.Changed FPFDMAX conditions in Table 37 and Table 38. Updated the GTP Transceiver
Specifications section, moved the GTP Transceiver DC characteristics section to the overall DC
Characteristics section, and added the GTP Transceiver Protocol Jitter Characteristics section. In
Table 65, updated Note 1. In Table 66, updated TPOR
.
02/01/2013
1.5
Updated the AC Switching Characteristics based upon the 14.4/2012.4 device pack for ISE 14.4 and
Vivado 2012.4, both at v1.07 for the -3, -2, -2L (1.0V), -1 speed specifications, and v1.05 for the -2L
(0.9V) speed specifications throughout the document. Production changes to Table 13 and Table 14
for -3, -2, -2L (1.0V), -1 speed specifications.
Revised IDCIN and IDCOUT and added Note 5 in Table 1. Added Note 2 to Table 2. Updated Table 5.
Added minimum current specifications to Table 6. Removed SSTL12 and HSTL_I_12 from Table 8.
Removed DIFF_SSTL12 from Table 10. Updated Table 13. Added a 2:1 memory controller section to
Table 16. Updated Note 1 in Table 34. Revised Table 36. Updated Note 1 and Note 2 in Table 49.
Updated DVPPIN in Table 50. Updated VIDIFF in Table 51. Removed TLOCK and TPHASE and revised
F
V
GCLK in Table 54. Updated TDLOCK in Table 55. Updated Table 56. In Table 57, updated TRTX, TFTX,
TXOOBVDPP , and revised Note 1 through Note 7. In Table 58, updated RXSST and RXPPMTOL and
revised Note 4 through Note 7. In Table 63, revised and added Note 1.
Revised the maximum external channel input ranges in Table 65. In Table 66, revised FMCCK and
added the Internal Configuration Access Port section.
04/17/2013
1.6
Updated the AC Switching Characteristics based upon v1.07 of the ISE 14.5 and Vivado 2013.1 for the
-3, -2, -2L (1.0V), and -1 speed specifications, and v1.05 for the -2L (0.9V) speed specifications.
Production changes to Table 13 and Table 14 for -2L (0.9V) speed specifications.
In Table 1, revised VIN (I/O input voltage) to match values in Table 4 and combined Note 4 with old Note
5 and then added new Note 5. Revised VIN description, removed Note 10, and added Note 7 in Table 2.
Updated first 3 rows in Table 4. Also revised PCI33_3 voltage minimum in Table 8 to match values in
Table 1 and Table 4. Added Note 1to Table 11. RemovedNote 1 from Table 14. Updated Table 16 title.
Throughout the data sheet (Table 28, Table 29, and Table 44) removed the obvious note “A Zero “0”
Hold Time listing indicates no hold time or a negative hold time.”
09/04/2013
11/27/2013
1.7
1.8
Added new Artix-7 devices (XC7A35T, XC7A50T, and XC7A75T) throughout. In Table 1, updated IDCIN
and IDCOUT for cases when floating, at VMGTAVTT, or GND. Added back Note 1 to Table 14. Added CPG
package to Table 50 and Table 52.
Added automotive and expanded temperature range Artix-7 devices throughout. Added -1M and -1Q
speed grades throughout. Added reference to 7 Series FPGAs Overview, Defense-Grade 7 Series
FPGAs Overview, and XA Artix-7 FPGAs Overview in Introduction. In Table 2, added junction
temperature operating ranges for expanded (Q) and military (M) devices, and added Note 3. In Table 3,
removed commercial (C), industrial (I), and extended (E) from descriptions of RIN_TERM. Updated
temperature ranges in Table 4. Removed notes from Table 6. Added TJ = 125°C to Conditions column
for TVCCO2VCCAUX in Table 7. In AC Switching Characteristics, updated first paragraph, added
Table 12, and added -1Q/-1M speed grades to other tables in this section. In Table 52, added RB and
RS packages, and updated FGTPMAX. In Table 65, updated ADC Accuracy, On-Chip Sensors, XADC
Reference sections and notes. Added TUSRCCLKO and FDNACK to Table 66.
DS181 (v1.25) June 18, 2018
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