Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 66: Configuration Switching Characteristics (Cont’d)
Speed Grade
-1
Symbol
Description
1.0V
0.95V
-1LI
0.9V
-2LE
Units
-3
-2/-2LE
Device DNA Access Port
FDNACK
DNA access port (DNA_PORT)
100.00
100.00
100.00
100.00
70.00
MHz, Max
Notes:
1. To support longer delays in configuration, use the design solutions described in 7 Series FPGA Configuration User Guide (UG470).
2. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
eFUSE Programming Conditions
Table 67 lists the programming conditions specifically for eFUSE. For more information, see 7 Series FPGA Configuration User
Guide (UG470).
(1)
Table 67: eFUSE Programming Conditions
Symbol
Description
Min
–
Typ
–
Max
115
125
Units
mA
IFS
Tj
VCCAUX supply current
Temperature range
15
–
°C
Notes:
1. The FPGA must not be configured during eFUSE programming.
Revision History
The following table shows the revision history for this document:
Date
Version
1.0
Description
09/26/2011
11/07/2011
Initial Xilinx release.
1.1
Revised the VOCM specification in Table 11. Updated the AC Switching Characteristics based upon the
ISE 13.3 software v1.02 speed specification throughout document including Table 13 and Table 14.
Added MMCM_TFBDELAY while adding MMCM_ to the symbol names of a few specifications in
Table 37 and PLL to the symbol names in Table 38. In Table 39 through Table 46, updated the pin-to-
pin description with the SSTL15 standard. Updated units in Table 46.
02/13/2012
1.2
Updated the Artix-7 family of devices listed throughout the entire data sheet. Updated the AC Switching
Characteristics based upon the ISE 13.4 software v1.03 for the -3, -2, and -1 speed grades and v1.00
for the -2L speed grade.
Updated summary description on page 1. In Table 2, revised VCCO for the 3.3V HR I/O banks and
updated Tj. Updated the notes in Table 5. Added MGTAVCC and MGTAVTT power supply ramp times
to Table 7. Rearranged Table 8, added Mobile_DDR, HSTL_I_18, HSTL_II_18, HSUL_12,
SSTL135_R, SSTL15_R, and SSTL12 and removed DIFF_SSTL135, DIFF_SSTL18_I,
DIFF_SSTL18_II, DIFF_HSTL_I, and DIFF_HSTL_II. Added Table 9 and Table 10. Revised the
specifications in Table 11. Revised VIN in Table 50. Updated the eFUSE Programming Conditions
section and removed the endurance table. Added the table. Revised FTXIN and FRXIN in Table 56.
Revised ICCADC and updated Note 1 in Table 65. Revised DDR LVDS transmitter data width in
Table 15. Removed notes from Table 27 as they are no longer applicable. Updated specifications in
Table 66. Updated Note 1 in Table 36.
DS181 (v1.25) June 18, 2018
www.xilinx.com
Product Specification
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