Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 37: GTH Transceiver Receiver Switching Characteristics
Symbol Description
Min
8000
–200
Typ
–
Max
–
Units
UI
RXRL
RXPPMTOL
SJ Jitter Tolerance(1)(2)(3)(4)
Run length (CID)
Data/REFCLK PPM offset tolerance
–
200
ppm
JT_SJ11.18
JT_SJ10.32
JT_SJ9.95
JT_SJ2.667
JT_SJ2.48
Sinusoidal Jitter
11.18 Gb/s
10.32 Gb/s
9.95 Gb/s
2.667 Gb/s
2.48 Gb/s
0.3
0.3
0.3
0.5
0.5
–
–
–
–
–
–
–
–
–
–
UI
UI
UI
UI
UI
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Sinusoidal Jitter
Notes:
1. These values are NOT intended for protocol specific compliance determinations.
–12
2. All jitter values are based on a bit error ratio of 1e
.
3. The frequency of the injected sinusoidal jitter is 80 MHz.
4. High-frequency jitter tolerance including 6 db of channel loss at a high frequency of the data rate divided by two.
Ethernet MAC Switching Characteristics
Consult UG368:Virtex-6 FPGA Embedded Tri-mode Ethernet MAC User Guide for further information.
Table 38: Maximum Ethernet MAC Performance
Speed Grade
Symbol
Description
Conditions
Units
-3
2.5(1)
25(2)
125
-2
2.5(1)
25(2)
125
-1
2.5(1)
25(2)
125
-1L
2.5(1)
25(2)
125
62.5
N/A
N/A
2.5
FTEMACCLIENT Client interface maximum
frequency
10 Mb/s – 8-bit width
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
100 Mb/s – 8-bit width
1000 Mb/s – 8-bit width
1000 Mb/s – 16-bit width
2000 Mb/s – 16-bit width
2500 Mb/s – 16-bit width
10 Mb/s – 4-bit width
62.5
125
62.5
125
62.5
125
156.25
2.5
156.25
2.5
156.25
2.5
FTEMACPHY
Physical interface maximum
frequency
100 Mb/s – 4-bit width
1000 Mb/s – 8-bit width
2000 Mb/s – 8-bit width
2500 Mb/s – 8-bit width
25
25
25
25
125
125
125
125
N/A
N/A
250
250
250
312.5
312.5
312.5
Notes:
1. When not using clock enable, the F
2. When not using clock enable, the F
is lowered to 1.25 MHz.
is lowered to 12.5 MHz.
MAX
MAX
DS152 (v3.6) March 18, 2014
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Product Specification
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