Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
(1)
Table 35: GTH Transceiver User Clock Switching Characteristics
Speed Grade
-2
Symbol
Description
Conditions
Units
-3
-1
FTXOUT
FRXOUT
TXUSERCLKOUT maximum frequency
RXUSERCLKOUT maximum frequency
350
350
350
280
350
280
175
140
170
350
280
350
280
175
140
170
350
323
323
323
258
323
258
162
129
157
323
258
323
258
162
129
157
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
350
16-bit data path
350
20-bit data path
32-bit data path
40-bit data path
64-bit data path
80-bit data path
64B/66B-bit data path
16-bit data path
20-bit data path
32-bit data path
40-bit data path
64-bit data path
80-bit data path
64B/66B-bit data path
280
350
FTXIN
TXUSERCLKIN maximum frequency
280
175
140
170
350
280
350
FRXIN
RXUSERCLKIN maximum frequency
280
175
140
170
Notes:
1. Clocking must be implemented as described in UG371:Virtex-6 FPGA GTH Transceivers User Guide.
Table 36: GTH Transceiver Transmitter Switching Characteristics
Symbol
Description
TX Rise time
Condition
20%–80%
Min
–
Typ
50(3)
50(3)
–
Max
–
Units
ps
TRTX
TFTX
TX Fall time
80%–20%
–
–
ps
TLLSKEW
Transmitter Output Jitter(1)(2)
TX lane-to-lane skew
within one GTH Quad
–
300
ps
TJ11.18
DJ11.18
TJ10.3125
DJ10.3125
TJ9.953
DJ9.953
TJ2.667
DJ2.667
TJ2.488
DJ2.488
Total Jitter
11.181 Gb/s
10.3125 Gb/s
9.953 Gb/s
2.667 Gb/s
2.488 Gb/s
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.280
0.170
0.280
0.170
0.280
0.170
0.110
0.060
0.110
0.060
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Notes:
1. These values are NOT intended for protocol specific compliance determinations.
-12
2. All jitter values are based on a bit-error ratio of 1e
.
3. Rise and fall times are specified at the transmitter package balls.
DS152 (v3.6) March 18, 2014
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Product Specification
21
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