Spartan-3E FPGA Family: Functional Description
SPI serial Flash PROMs and the Atmel AT45DB-series
Data Flash PROMs using the Platform Cable USB, Xilinx
Parallel IV, or other compatible programming cable.
Byte-Wide Peripheral Interface (BPI) Parallel
Flash Mode
For additional information, refer to the “Master BPI Mode”
chapter in UG332.
In Byte-wide Peripheral Interface (BPI) mode
(M[2:0] = <0:1:0> or <0:1:1>), a Spartan-3E FPGA
configures itself from an industry-standard parallel NOR
Flash PROM, as illustrated in Figure 58. The FPGA
generates up to a 24-bit address lines to access an
attached parallel Flash. Only 20 address lines are
generated for Spartan-3E FPGAs in the TQ144 package.
Similarly, the XC3S100E FPGA in the CP132 package only
has 20 address lines while the XC3S250E and XC3S500E
FPGAs in the same package have 24 address lines. When
using the VQ100 package, the BPI mode is not available
when using parallel NOR Flash, but is supported using
parallel Platform Flash (XCFxxP).
The BPI configuration interface is primarily designed for
standard parallel NOR Flash PROMs and supports both
byte-wide (x8) and byte-wide/halfword (x8/x16) PROMs.
The interface functions with halfword-only (x16) PROMs,
but the upper byte in a portion of the PROM remains
unused. For configuration, the BPI interface does not
require any specific Flash PROM features, such as boot
block or a specific sector size.
The BPI interface also functions with Xilinx parallel Platform
Flash PROMs (XCFxxP), although the FPGA’s address
lines are left unconnected.
The BPI interface also works equally wells with other
asynchronous memories that use a similar SRAM-style
interface such as SRAM, NVRAM, EEPROM, EPROM, or
masked ROM.
NAND Flash memory is commonly used in memory cards
for digital cameras. Spartan-3E FPGAs do not configure
directly from NAND Flash memories.
The FPGA’s internal oscillator controls the interface timing
and the FPGA supplies the clock on the CCLK output pin.
However, the CCLK signal is not used in single FPGA
applications. Similarly, the FPGA drives three pins Low
during configuration (LDC[2:0]) and one pin High during
configuration (HDC) to the PROM’s control inputs.
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
84
XILINX [ XILINX, INC ]
