Spartan-3E FPGA Family: Functional Description
Table 59: Byte-Wide Peripheral Interface (BPI) Connections (Cont’d)
Pin Name
HDC
FPGA Direction
Description
PROM Write Enable
During Configuration
After Configuration
User I/O
Output
Connect to PROM write-enable
input (WE#). FPGA drives this
signal High throughout
configuration.
LDC2
Output
Output
PROM Byte Mode
This signal is not used for x8
PROMs. For PROMs with a x8/x16 after configuration to use a
data width control, connect to
PROM byte-mode input (BYTE#).
See Precautions Using x8/x16
Flash PROMs. FPGA drives this
signal Low throughout
UserI/O. Drive this pin High
D
x8/x16 PROM in x16 mode.
configuration.
A[23:0]
Address
Connect to PROM address inputs. User I/O
High-order address lines may not
be available in all packages and
not all may be required. Number of
address lines required depends on
the size of the attached Flash
PROM. FPGA address generation
controlled by M0 mode pin.
Addresses presented on falling
CCLK edge.
Only 20 address lines are available
in TQ144 package.
D[7:0]
Input
Data Input
FPGA receives byte-wide data on User I/O. If bitstream option
these pins in response the address Persist=Yes, becomes
presented on A[23:0]. Data
part of SelectMap parallel
captured by FPGA on rising edge peripheral interface.
of CCLK.
CSO_B
Output
Chip Select Output. Active Low.
Not used in single FPGA
User I/O
applications. In a daisy-chain
configuration, this pin connects to
the CSI_B pin of the next FPGA in
the chain. If HSWAP = 1 in a
multi-FPGA daisy-chain
application, connect this signal to a
4.7 kΩ pull-up resistor to VCCO_2.
Actively drives Low when selecting
a downstream device in the chain.
BUSY
CCLK
Output
Output
Busy Indicator. Typicallyonly used Not used during configuration but User I/O. If bitstream option
after configuration, if bitstream
actively drives.
Persist=Yes, becomes
part of SelectMap parallel
peripheral interface.
option Persist=Yes.
Configuration Clock. Generated Not used in single FPGA
User I/O. If bitstream option
applications but actively drives. In Persist=Yes, becomes
by FPGA internal oscillator.
Frequency controlled by
a daisy-chain configuration, drives part of SelectMap parallel
ConfigRate bitstream generator
the CCLK inputs of all other
peripheral interface.
option. If CCLK PCB trace is long or FPGAs in the daisy-chain.
has multiple connections, terminate
this output to maintain signal
integrity. See CCLK Design
Considerations.
INIT_B
Open-drain
InitializationIndicator.ActiveLow. Active during configuration. If CRC User I/O. If unused in the
application, drive INIT_B
configuration, FPGA drives INIT_B High.
bidirectional I/O Goes Low at start of configuration error detected during
during the Initialization memory
clearing process. Released at the Low.
end of memory clearing, when the
mode select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 kΩ pull-up
resistor to VCCO_2.
DS312 (v4.2) December 14, 2018
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Product Specification
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XILINX [ XILINX, INC ]
