Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 58
+1.2V
V
VCCINT
HSWAP
VCCO_0
VCCO_0
P
I
VCCO
VCCO_1
LDC0
V
x8 or
x8/x16
Flash
PROM
CE#
LDC1
OE#
HDC
WE#
BYTE#
LDC2
Not available
in VQ100
D
A[16:0]
package
DQ[15:7]
BPI Mode
VCCO_2
D[7:0]
V
‘0’
‘1’
A
M2
M1
M0
DQ[7:0]
A[n:0]
A[23:17]
GND
V
Spartan-3E
BUSY
CCLK
FPGA
‘0’
‘0’
CSI_B
CSO_B
INIT_B
RDWR_B
+2.5V
JTAG
+2.5V
VCCAUX
TDO
+2.5V
TDI
TDI
TMS
TCK
TDO
TMS
TCK
PROG_B
DONE
GND
PROG_B
Recommend
open-drain
driver
DS312-2_49_082009
Figure 58: Byte-wide Peripheral Interface (BPI) Mode Configured from Parallel NOR Flash PROMs
A
During configuration, the value of the M0 mode pin
determines how the FPGA generates addresses, as shown
Table 58. When M0 = 0, the FPGA generates addresses
starting at 0 and increments the address on every falling
CCLK edge. Conversely, when M0 = 1, the FPGA
generates addresses starting at 0xFF_FFFF(all ones) and
decrements the address on every falling CCLK edge.
Table 58: BPI Addressing Control
M2
M1
M0
0
Start Address
0
Addressing
Incrementing
Decrementing
0
1
1
0xFF_FFFF
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
85
XILINX [ XILINX, INC ]
