Spartan-3E FPGA Family: Functional Description
Table 59: Byte-Wide Peripheral Interface (BPI) Connections (Cont’d)
Pin Name
DONE
FPGA Direction
Description
During Configuration
After Configuration
Open-drain
FPGA Configuration Done. Low
Low indicates that the FPGA is not Pulled High via external
yet configured.
bidirectional I/O during configuration. Goes High
whenFPGAsuccessfullycompletes
configuration. Requires external
pull-up. When High,
indicates that the FPGA is
successfully configured.
330 Ω pull-up resistor to 2.5V.
PROG_B
Input
Program FPGA. Active Low. When Must be High to allow configuration Drive PROG_B Low and
asserted Low for 500 ns or longer, to start.
forces the FPGA to restart its
configuration process by clearing
configuration memory and resetting
the DONE and INIT_B pins once
PROG_B returns High.
release to reprogram
FPGA. Hold PROG_B to
force FPGA I/O pins into
Hi-Z, allowing direct
programming access to
Flash PROM pins.
Recommend external 4.7 kΩ
pull-up resistor to 2.5V. Internal
pull-up value may be weaker (see
Table 78). If driving externally with a
3.3V output, use an open-drain or
open-collector driver or use a
current limiting series resistor.
Power-On Precautions if 3.3V Supply is Last in Sequence
for a similar description of the issue for SPI Flash PROMs.
Voltage Compatibility
V
The FPGA’s parallel Flash interface signals are within
I/O Banks 1 and 2. The majority of parallel Flash PROMs
use a single 3.3V supply voltage. Consequently, in most
cases, the FPGA’s VCCO_1 and VCCO_2 supply voltages
must also be 3.3V to match the parallel Flash PROM. There
are some 1.8V parallel Flash PROMs available and the
FPGA interfaces with these devices if the VCCO_1 and
VCCO_2 supplies are also 1.8V.
Supported Parallel NOR Flash PROM Densities
Table 60 indicates the smallest usable parallel Flash PROM
to program a single Spartan-3E FPGA. Parallel Flash
density is specified in bits but addressed as bytes. The
FPGA presents up to 24 address lines during configuration
but not all are required for single FPGA applications.
Table 60 shows the minimum required number of address
lines between the FPGA and parallel Flash PROM. The
actual number of address line required depends on the
density of the attached parallel Flash PROM.
Power-On Precautions if PROM Supply is Last in
Sequence
Like SPI Flash PROMs, parallel Flash PROMs typically
require some amount of internal initialization time when the
supply voltage reaches its minimum value.
A multiple-FPGA daisy-chained application requires a
parallel Flash PROM large enough to contain the sum of the
FPGA file sizes. An application can also use a larger-density
parallel Flash PROM to hold additional data beyond just
FPGA configuration data. For example, the parallel Flash
PROM can also contain the application code for a MicroBlaze
RISC processor core implemented within the Spartan-3E
FPGA. After configuration, the MicroBlaze processor can
execute directly from external Flash or can copy the code to
other, faster system memory before executing the code.
The PROM supply voltage also connects to the FPGA’s
VCCO_2 supply input. In many systems, the PROM supply
feeding the FPGA’s VCCO_2 input is valid before the
FPGA’s other V
and V
supplies, and
CCINT
CCAUX
consequently, there is no issue. However, if the PROM
supply is last in the sequence, a potential race occurs
between the FPGA and the parallel Flash PROM. See
Table 60: Number of Bits to Program a Spartan-3E FPGA and Smallest Parallel Flash PROM
Uncompressed
File Sizes (bits)
Smallest Usable
Parallel Flash PROM
Minimum Required
Address Lines
Spartan-3E FPGA
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
581,344
1,353,728
2,270,208
3,841,184
5,969,696
1 Mbit
2 Mbit
4 Mbit
4 Mbit
8 Mbit
A[16:0]
A[17:0]
A[18:0]
A[18:0]
A[19:0]
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
88
XILINX [ XILINX, INC ]
