Spartan-3E FPGA Family: Functional Description
for its three power supplies — V
, V
, and V
CCAUX CCO
Voltage Compatibility
CCINT
to I/O Bank 2 (VCCO_2) — to reach their respective
Available SPI Flash PROMs use a single 3.3V supply
voltage. All of the FPGA’s SPI Flash interface signals are
within I/O Bank 2. Consequently, the FPGA’s VCCO_2
supply voltage must also be 3.3V to match the SPI Flash
PROM.
power-on thresholds before beginning the configuration
process.
The SPI Flash PROM is powered by the same voltage
supply feeding the FPGA's VCCO_2 voltage input, typically
3.3V. SPI Flash PROMs specify that they cannot be
Power-On Precautions if 3.3V Supply is Last in
Sequence
accessed until their V supply reaches its minimum data
CC
sheet voltage, followed by an additional delay. For some
devices, this additional delay is as little as 10 µs as shown in
Table 56. For other vendors, this delay is as much as 20 ms.
Spartan-3E FPGAs have a built-in power-on reset (POR)
circuit, as shown in Figure 66, page 103. The FPGA waits
Table 56: Example Minimum Power-On to Select Times for Various SPI Flash PROMs
Data Sheet Minimum Time from VCC min to Select = Low
SPI Flash PROM
Part Number
Vendor
Symbol
TVSL
Value
10
Units
μs
STMicroelectronics
Spansion
M25Pxx
S25FLxxxA
NX25xx
tPU
10
ms
μs
NexFlash
TVSL
10
Macronix
MX25Lxxxx
SST25LFxx
tVSL
10
μs
Silicon Storage Technology
TPU-READ
10
μs
Programmable Microelectronics
Corporation
Pm25LVxxx
TVCS
tVCSL
50
μs
Atmel Corporation
AT45DBxxxD
AT45DBxxxB
30
20
μs
ms
In many systems, the 3.3V supply feeding the FPGA's
VCCO_2 input is valid before the FPGA's other V
supply is last in the sequence, a potential race occurs
between the FPGA and the SPI Flash PROM, as shown in
Figure 55.
and
CCINT
V
supplies, and consequently, there is no issue.
CCAUX
However, if the 3.3V supply feeding the FPGA's VCCO_2
X-Ref Target - Figure 55
3.3V Supply
SPI Flash cannot be selected
SPI Flash PROM
minimum voltage
SPI Flash available for
read operations
SPI Flash
PROM CS
SPI Flash PROM must
be ready for FPGA
access, otherwise delay
FPGA configuration
FPGA VCCO_2 minimum
Power On Reset Voltage
(t
)
delay
VSL
(VCCO2T
)
FPGA accesses
SPI Flash PROM
FPGA initializes configuration
(V
, V
CCINT CCAUX
memory (TPOR
)
already valid)
Time
DS312-2_50b_110206
Figure 55: SPI Flash PROM/FPGA Power-On Timing if 3.3V Supply is Last in Power-On Sequence
If the FPGA's V
valid, then the FPGA waits for VCCO_2 to reach its
minimum threshold voltage before starting configuration.
and V
supplies are already
CCAUX
respective Power On Reset (POR) thresholds, the FPGA
starts the configuration process and begins initializing its
internal configuration memory. Initialization requires
CCINT
This threshold voltage is labeled as V
in Table 74 of
approximately 1 ms (T
, minimum in Table 111 of
CCO2T
POR
Module 3 and ranges from approximately 0.4V to 1.0V,
substantially lower than the SPI Flash PROM's minimum
voltage. Once all three FPGA supplies reach their
Module 3, after which the FPGA de-asserts INIT_B, selects
the SPI Flash PROM, and starts sending the appropriate
read command. The SPI Flash PROM must be ready for
DS312 (v4.2) December 14, 2018
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Product Specification
80
XILINX [ XILINX, INC ]
