Spartan-3E FPGA Family: Functional Description
Daisy-Chaining
If the application requires multiple FPGAs with different
configurations, then configure the FPGAs using a daisy
chain, as shown in Figure 57. Daisy-chaining from a single
SPI serial Flash PROM is supported in Stepping 1 devices.
It is not supported in Stepping 0 devices. Use SPI Flash
mode (M[2:0] = <0:0:1>) for the FPGA connected to the
Platform Flash PROM and Slave Serial mode
diagram—finishes loading its configuration data from the
SPI Flash PROM, the master device uses its DOUT output
pin to supply data to the next device in the daisy-chain, on
the falling CCLK edge.
Design Note
SPI mode daisy chains are supported only in Stepping 1
silicon versions.
(M[2:0] = <1:1:1>) for all other FPGAs in the daisy-chain.
After the master FPGA—the FPGA on the left in the
X-Ref Target - Figure 57
SPI-based daisy-chaining is
only supported in Stepping 1.
!
CCLK
+1.2V
+1.2V
+3.3V
SPI
Serial
VCCINT
Flash
VCCINT
P
P
HSWAP
VCCO_0
VCCO_0
P
HSWAP
VCCO_0
VCCO_2
VCCO_0
I
VCC
DATA_IN
VCCO_2
MOSI
+3.3V
+3.3V
Slave
Serial
Mode
SPI Mode
DIN
DATA_OUT
SELECT
‘0’
‘0’
‘1’
M2
M1
M0
CSO_B
‘1’
‘1’
‘1’
M2
M1
M0
W
WR_PROTECT
HOLD
‘1’
Spartan-3E
FPGA
CLOCK
Spartan-3E
FPGA
Variant Select
GND
‘1’
S
VS2
VS1
VS0
‘1’
CCLK
DOUT
INIT_B
CCLK
DIN
DOUT
INIT_B
DOUT
+2.5V
JTAG
TDI
VCCAUX
TDO
+2.5V
VCCAUX
TDO
+2.5V
TDI
TDI
TMS
TCK
TDO
TMS
TCK
TMS
TCK
+2.5V
+3.3V
PROG_B
DONE
PROG_B
DONE
GND
GND
PROG_B
PROG_B
Recommend
open-drain
driver
TCK
TMS
DONE
INIT_B
DS312-2_48_082009
Figure 57: Daisy-Chaining from SPI Flash Mode (Stepping 1)
In-system programming support is available from some
third-party PROM programmers using a socket adapter with
attached wires. To gain access to the SPI Flash signals,
drive the FPGA’s PROG_B input Low with an open-drain
driver. This action places all FPGA I/O pins, including those
attached to the SPI Flash, in high-impedance (Hi-Z). If the
HSWAP input is Low, the I/Os have pull-up resistors to the
Programming Support
For successful daisy-chaining, the DONE_cycle
configuration option must be set to cycle 5 or sooner. The
default cycle is 4. See Table 69 and the Start-Up section for
additional information.
I
In production applications, the SPI Flash PROM is
V
input on their respective I/O bank. The external
usually pre-programmed before it is mounted on the printed
circuit board. The Xilinx ISE development software
produces industry-standard programming files that can be
used with third-party gang programmers. Consult your
specific SPI Flash vendor for recommended production
programming solutions.
CCO
programming hardware then has direct access to the SPI
Flash pins. The programming access points are highlighted
in the gray box in Figure 53, Figure 54, and Figure 57.
Beginning with the Xilinx ISE 8.2i software release, the
iMPACT programming utility provides direct, in-system
prototype programming support for STMicro M25P-series
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
83
XILINX [ XILINX, INC ]
