Spartan-3E FPGA Family: Functional Description
During the configuration process, CCLK is controlled by the
FPGA and limited to the frequencies generated by the
FPGA. After configuration, the FPGA application can use
other clock signals to drive the CCLK pin and can further
optimize SPI-based communication.
Refer to the individual SPI peripheral data sheet for specific
interface and communication protocol requirements.
X-Ref Target - Figure 56
Spartan-3E FPGA
SPI Serial Flash PROM
FFFFF
User Data
MOSI
DIN
DATA_IN
FPGA-based
SPI Master
MicroBlaze
DATA_OUT
Code
CCLK
CLOCK
FPGA
Configuration
CSO_B
SELECT
+3.3V
0
User I/O
SPI Peripherals
- A/D Converter
DATA_IN
DATA_OUT
CLOCK
- D/A Converter
- CAN Controller
- Displays
- Temperature Sensor
- ASSP
SELECT
DS312-2_47_082009
To other SPI slave peripherals
Figure 56: Using the SPI Flash Interface After Configuration
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
82
XILINX [ XILINX, INC ]
