Spartan-3E FPGA Family: Functional Description
Table 55: Serial Peripheral Interface (SPI) Connections (Cont’d)
FPGA
Direction
Pin Name
Description
During Configuration
After Configuration
VS[2:0]
Input
Variant Select. Instructs the FPGA how Must be at the logic levels shown User I/O
to communicate with the attached SPI in Table 53. Sampled when
FlashPROM. See DesignConsiderations INIT_B goes High.
for the HSWAP, M[2:0], and VS[2:0] Pins.
S
MOSI
Output
Serial Data Output.
FPGA sends SPI Flash memory User I/O
read commands and starting
address to the PROM’s serial
data input.
DIN
Input
Serial Data Input.
FPGA receives serial data from User I/O
PROM’s serial data output.
CSO_B
Output
Chip Select Output. Active Low.
Connects to the SPI Flash
PROM’s chip-select input. If
Drive CSO_B High after
configuration to disable the
HSWAP = 1, connect this signal SPI Flash and reclaim the
to a 4.7 kΩ pull-up resistor to
3.3V.
MOSI, DIN, and CCLK pins.
Optionally, re-use this pin
and MOSI, DIN, and CCLK
to continue communicating
with SPI Flash.
CCLK
Output
Output
Configuration Clock. Generated by
FPGA internal oscillator. Frequency
controlled by ConfigRate bitstream
generator option. If CCLK PCB trace is
long or has multiple connections,
terminate this output to maintain signal
integrity. See CCLK Design
Drives PROM’s clock input.
User I/O
Considerations.
DOUT
INIT_B
Serial Data Output.
Actively drives. Not used in
single-FPGA designs. In a
daisy-chain configuration, this
pin connects to DIN input of the
next FPGA in the chain.
User I/O
Open-drain Initialization Indicator. Active Low.
bidirectional Goes Low at start of configuration during SPI Flash PROM requires
Active during configuration. If
User I/O. If unused in the
application, drive INIT_B
I/O
Initialization memory clearing process.
Released at end of memory clearing,
when mode select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 kΩ pull-up
resistor to VCCO_2.
> 2 ms to awake after powering High.
on, hold INIT_B Low until PROM
is ready. If CRC error detected
during configuration, FPGA
drives INIT_B Low.
DONE
Open-drain FPGA Configuration Done. Low during Low indicates that the FPGA is Pulled High via external
bidirectional configuration. Goes High when FPGA
not yet configured.
pull-up. When High,
I/O
successfully completes configuration.
Requires external 330 Ω pull-up resistor
to 2.5V.
indicates that the FPGA
successfully configured.
PROG_B
Input
Program FPGA. Active Low. When
Must be High to allow
Drive PROG_B Low and
release to reprogram FPGA.
Hold PROG_B to force
FPGA I/O pins into Hi-Z,
allowing direct programming
access to SPI Flash PROM
pins.
asserted Low for 500 ns or longer, forces configuration to start.
the FPGA to restart its configuration
process by clearing configuration
memory and resetting the DONE and
INIT_B pins once PROG_B returns High.
Recommend external 4.7 kΩ pull-up
resistor to 2.5V. Internal pull-up value
may be weaker (see Table 78). If driving
externally with a 3.3V output, use an
open-drain or open-collector driver or use
a current limiting series resistor.
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
79
XILINX [ XILINX, INC ]
